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r01ds0192ej0200 rev. 2.00 page 1 of 149 feb 21, 2014 rl78/l1c renesas mcu integrated lcd controller/driver, 12-bit resolution a/d converter, usb 2.0 controller (function), true low power platform (as low as 112.5 ? a/mhz, and 0.68 ? a for rtc2 + lvd), 1.6 v to 3.6 v operation, 64 to 256 kbyte flash, 33 dmips at 24 mhz, for all lcd based applications datasheet 1. outline 1.1 features ultra-low power technology ? 1.6 v to 3.6 v operation from a single supply ? stop (ram retained): 0.25 ? a, (lvd enabled): 0.31 ? a ? halt (rtc2 + lvd): 0.68 ? a ? supports snooze ? operating: 112.5 ? a/mhz 16-bit rl78 cpu core ? delivers 33 dmips at maximum operating frequency of 24 mhz ? instruction execution: 86% of instructions can be executed in 1 to 2 clock cycles ? cisc architecture (harvard) with 3-stage pipeline ? multiply signed & unsigned: 16 ? 16 to 32-bit result in 1 clock cycle ? mac: 16 ? 16 to 32-bit result in 2 clock cycles ? 16-bit barrel shifter for shift & rotate in 1 clock cycle ? 1-wire on-chip debug function code flash memory ? density: 64 to 256 kb ? block size: 1 kb ? on-chip single voltage flash memory with protection from block erase/writing ? self-programming with secure boot swap function and flash shield window function data flash memory ? data flash with background operation ? data flash size: 8 kb ? erase cycles: 1 million (typ.) ? erase/programming voltage: 1.8 v to 3.6 v ram ? 8 kb to 16 kb size options ? supports operands or instructions ? back-up retention in all modes high-speed on-chip oscillator ? 24 mhz with +/- 1% accuracy over voltage (1.8 v to 3.6 v) and temperature (-20c to +85c) ? pre-configured settings: 48 mhz, 24 mhz, 16 mhz, 12 mhz, 8 mhz, 6 mhz, 4 mhz, 3 mhz, 2 mhz, 1 mhz (typ.) ? 48 mhz for usb, 48 mhz for timer kb2 reset and supply management ? power-on reset (por) monitor/generator ? low voltage detection (lvd) with 12 setting options (interrupt and/or reset function) lcd controller/driver ? up to 56 seg ? 4 com or 52 seg ? 8 com ? supports capacitor split method, internal voltage boost method and resistance division method ? supports waveform types a and b ? supports lcd contrast adjustment (18 steps) ? supports lcd blinking usb ? complying with usb 2.0 ? corresponding to full-speed transfer (12 mbps) and low-speed (1.5 mbps) ? complying with battery charging specification revision 1.2 ? supports usb function controller data transfer controller (dtc) ? 33 sources & 24 different settings ? transfer data: 8 bits/16 bits ? normal mode and repeat mode event link controller (elc) ? reduce interrupt intervention ? link 31 events to specified peripheral function multiple communication interfaces ?up to 4 ? i 2 c master ?up to 1 ? i 2 c multi-master ?up to 4 ? csi (7-, 8-bit) ?up to 4 ? uart (7-, 8-, 9-bit) ?up to 1 ? lin extended-function timers ? multi-function 16-bit timer tau: up to 8 channels (remote control output available) ? multi-function 16-bit timer kb2: 3 channels ? real-time clock 2 (rtc2): 1 channel (full calendar and alarm function with watch correction function) ? 12-bit interval timer: 1 channel ? 15 khz watchdog timer: 1 channel (window function) rich analog ? adc: up to 13 channels, 8/12-bit resolution, 3.375 ? s minimum conversion time ? supports 1.6 v ? d/a converter: 2 channels, 8-bit resolution ?2 ? window comparators, with elc connection ? internal voltage reference (1.45 v) ? on-chip temperature sensor safety features (iec or ul 60730 compliance) ? flash memory crc calculation ? ram parity error check ? ram write protection ? sfr write protection ? illegal memory access detection ? clock stop/ frequency detection ? adc self-test ? i/o port read back function (echo) general purpose i/o ? high-current (up to 20 ma per pin) ? open-drain, internal pull-up support operating ambient temperature ?t a : -40 to +85 c (a: consumer applications) ?t a : -40 to +105 c (g: industrial applications) package type and pin count ? 80-pin plastic lfqfp (12 ? 12 mm, 0.5 mm pitch) ? 85-pin plastic vflga (7 ? 7 mm, 0.65 mm pitch) ? 100-pin plastic lfqfp (14 ? 14 mm, 0.5 mm pitch) r01ds0192ej0200 rev. 2.00 feb 21, 2014
rl78/l1c 1. outline r01ds0192ej0200 rev. 2.00 page 2 of 149 feb 21, 2014 rom, ram capacities note this is about 15 kb when the self-programmi ng function and data flash function are used. products with usb flash rom data flash ram rl78/l1c 80 pins 85 pins 100 pins 256 kb 8 kb 16 kb note R5F110MJ r5f110nj r5f110pj 192 kb 8 kb 16 kb note r5f110mh r5f110nh r5f110ph 128 kb 8 kb 12 kb r5f110mg r5f110ng r5f110pg 96 kb 8 kb 10 kb r5f110mf r5f110nf r5f110pf 64 kb 8 kb 8 kb r5f110me r5f110ne r5f110pe products without usb flash rom data flash ram rl78/l1c 80 pins 85 pins 100 pins 256 kb 8 kb 16 kb note r5f111mj r5f111nj r5f111pj 192 kb 8 kb 16 kb note r5f111mh r5f111nh r5f111ph 128 kb 8 kb 12 kb r5f111mg r5f111ng r5f111pg 96 kb 8 kb 10 kb r5f111mf r5f111nf r5f111pf 64 kb 8 kb 8 kb r5f111me r5f111ne r5f111pe
rl78/l1c 1. outline r01ds0192ej0200 rev. 2.00 page 3 of 149 feb 21, 2014 1.2 ordering information products with usb pin count package fields of application orderable part number 80 pins 80-pin plastic lfqfp (12 ? 12 mm, 0.5 mm pitch) a r5f110meafb#30, r5f110mfafb#30, r5f110mgafb#30, r5f110mhafb#30, R5F110MJafb#30 r5f110meafb#50, r5f110mfafb#50, r5f110mgafb#50, r5f110mhafb#50, R5F110MJafb#50 g r5f110megfb#30, r5f110mfgfb#30, r5f110mggfb#30, r5f110mhgfb#30, R5F110MJgfb#30 r5f110megfb#50, r5f110mfgfb#50, r5f110mggfb#50, r5f110mhgfb#50, R5F110MJgfb#50 85 pins 85-pin plastic vflga (7 ? 7 mm, 0.65 mm pitch) a r5f110neala#u0, r5f110nfala#u0, r5f110ngala#u0, r5f110nhala#u0, r5f110njala#u0 r5f110neala#w0, r5f110nfala#w0, r5f110ngala#w0, r5f110nhala#w0, r5f110njala#w0 g r5f110negla#u0, r5f110nfgla#u0, r5f110nggla#u0, r5f110nhgla#u0, r5f110njgla#u0 r5f110negla#w0, r5f110nfgla#w0, r5f110ng gla#w0, r5f110nhgla#w0, r5f110njgla#w0 100 pins 100-pin plastic lfqfp (14 ? 14 mm, 0.5 mm pitch) a r5f110peafb#30, r5f110pfafb#30, r5f110pgafb#30, r5f110phafb#30, r5f110pjafb#30 r5f110peafb#50, r5f110pfafb#50, r5f110pgafb#50, r5f110phafb#50, r5f110pjafb#50 g r5f110pegfb#30, r5f110pfgfb#30, r5f110pggfb#30, r5f110phgfb#30, r5f110pjgfb#30 r5f110pegfb#50, r5f110pfgfb#50, r5f110pggfb#50, r5f110phgfb#50, r5f110pjgfb#50 products without usb pin count package fields of application orderable part number 80 pins 80-pin plastic lfqfp (12 ? 12 mm, 0.5 mm pitch) a r5f111meafb#30, r5f111mfafb#30, r5f111mgafb#30, r5f111mhafb#30, r5f111mjafb#30 r5f111meafb#50, r5f111mfafb#50, r5f111mgafb#50, r5f111mhafb#50, r5f111mjafb#50 g r5f111megfb#30, r5f111mfgfb#30, r5f111mggfb#30, r5f111mhgfb#30, r5f111mjgfb#30 r5f111megfb#50, r5f111mfgfb#50, r5f111mggfb#50, r5f111mhgfb#50, r5f111mjgfb#50 85 pins 85-pin plastic vflga (7 ? 7 mm, 0.65 mm pitch) a r5f111neala#u0, r5f111nfala#u0, r5f111ngala#u0, r5f111nhala#u0, r5f111njala#u0 r5f111neala#w0, r5f111nfala#w0, r5f111ngala#w0, r5f111nhala#w0, r5f111njala#w0 g r5f111negla#u0, r5f111nfgla#u0, r5f111 nggla#u0, r5f111nhgla#u0, r5f111njgla#u0 r5f111negla#w0, r5f111nfgla#w0, r5f111nggla#w0, r5f111nhgla#w0, r5f111njgla#w0 100 pins 100-pin plastic lfqfp (14 ? 14 mm, 0.5 mm pitch) a r5f111peafb#30, r5f111pfafb#30, r5f111pgafb#30, r5f111phafb#30, r5f111pjafb#30 r5f111peafb#50, r5f111pfafb#50, r5f111pgafb#50, r5f111phafb#50, r5f111pjafb#50 g r5f111pegfb#30, r5f111pfgfb#30, r5f111p ggfb#30, r5f111phgfb#30, r5f111pjgfb#30 r5f111pegfb#50, r5f111pfgfb#50, r5f111pggfb#50, r5f111phgfb#50, r5f111pjgfb#50
rl78/l1c 1. outline r01ds0192ej0200 rev. 2.00 page 4 of 149 feb 21, 2014 figure 1 - 1 part number, memory size, and package of rl78/l1c caution orderable part numbers are current as of when this manual was published. please make sure to refer to the relevant product page on the renesas website for the latest part numbers. packaging specification: #30: tray (lfqfp) #u0: tray (vflga) #50: embossed tape (lfqfp) #w0: embossed tape (vflga) r 5 f 1 1 0 p e a x x x f b # 3 0 part no. package type: fb: lfqfp, 0.50 mm pitch la: vflga, 0.65 mm pitch fields of application: a: consumer applications, t a = -40 to +85 c g: industrial applications, t a = -40 to +105 c rom capacity: e: 64 kb f: 96 kb g: 128 kb h: 192 kb j: 256 kb pin count: m: 80-pin n: 85-pin p: 100-pin rl78/l1c group 110: products with usb 111: products without usb memory type: f: flash memory renesas mcu renesas semiconductor product rom number (omitted with blank products)
rl78/l1c 1. outline r01ds0192ej0200 rev. 2.00 page 5 of 149 feb 21, 2014 1.3 pin configuration (top view) 1.3.1 80-pin products (with usb) ? 80-pin plastic lfqfp (12 ? 12 mm, 0.5 mm pitch) caution 1. connect the regc pin to v ss pin via a capacitor (0.47 to 1 ? f). caution 2. connect the u regc pin to v ss pin via a capacitor (0.33 ? f). remark 1. for pin identification, see 1.4 pin identification . remark 2. functions in parentheses in the above figure can be assi gned via settings in the peripher al i/o redirection register (pior). p11/rxd2/si20/sda20/seg41/vcout0 p10/intp7/pclbuz0/sck20/scl20/seg40 p27/ti05/to05/(intp5)/pclbuz1/seg39 p26/so00/txd0/tooltxd/seg38 p25/si00/rxd0/toolrxd/sda00/seg37 p24/sck00/scl00/seg36 p23/ti07/to07/seg35 p22/ti04/to04/seg34 p21/ani21/seg33 p20/ani20/seg32 p143/ani19/seg31 p142/ani18/seg30 p141/ani17/seg29 p140/ani16/seg28 u regc uv bus udm udp av dd av ss p70/kr7/seg12 p71/kr6/seg13 p72/kr5/tkbo20/seg14 p73/kr4/tkbo21/seg15 p74/kr3/tkbo10/seg16 p75/kr2/tkbo11/seg17 p76/kr1/tkbo00/seg18 p77/kr0/tkbo01/seg19 p30/ti03/to03/remoout/seg20 p31/intp3/rtc1hz/seg21 p32/ti01/to01/seg22 p33/intp4/sck30/scl30/seg23 p34/si30/rxd3/sda30/seg24 p35/so30/txd3/seg25 p125/v l3 /(ti06)/(to06) v l4 v l2 v l1 p126/capl/(ti04)/(to04) p127/caph/(ti03)/(to03)/(remoout) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 123 456 78910 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p152/ani2 p151/ani1/av refm p150/ani0/av refp p130 p46/ano1 p45/ano0 p44/ivref0 p43/(intp7)/ivcmp0 p40/tool0/(ti00)/(to00) reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss0 v dd0 p60/scla0/(ti01)/(to01) p61/sdaa0/(ti02)/(to02) p12/txd2/so20/seg42 p00/sck10/scl10/seg48 p01/si10/rxd1/sda10/seg49 p02/so10/txd1/(pclbuz0)/seg50 p03/ti00/to00/intp1/seg51 p04/intp2/seg52 p05/ti02/to02/seg53 p06/intp5/seg54 p07/ti06/to06/seg55 com0 com1 com2 com3 com4/seg0 com5/seg1 com6/seg2 com7/seg3 p50/seg4/intp6 p51/seg5 p52/seg6
rl78/l1c 1. outline r01ds0192ej0200 rev. 2.00 page 6 of 149 feb 21, 2014 1.3.2 80-pin products (without usb) ? 80-pin plastic lfqfp (fine pitch) (12 ? 12 mm, 0.5 mm pitch) caution connect the regc pin to v ss pin via a capacitor (0.47 to 1 ? f). remark 1. for pin identification, see 1.4 pin identification . remark 2. functions in parentheses in the above figure can be assi gned via settings in the peripher al i/o redirection register (pior). p11/rxd2/si20/sda20/seg41/vcout0 p10/intp7/pclbuz0/sck20/scl20/seg40 p27/ti05/to05/(intp5)/pclbuz1/seg39 p26/so00/txd0/tooltxd/seg38 p25/si00/rxd0/toolrxd/sda00/seg37 p24/sck00/scl00/seg36 p23/ti07/to07/seg35 p22/ti04/to04/seg34 p21/ani21/seg33 p20/ani20/seg32 p143/ani19/seg31 p142/ani18/seg30 p141/ani17/seg29 p140/ani16/seg28 p82 p83 p156/ani6 p155/ani5 av dd av ss p70/kr7/seg12 p71/kr6/seg13 p72/kr5/tkbo20/seg14 p73/kr4/tkbo21/seg15 p74/kr3/tkbo10/seg16 p75/kr2/tkbo11/seg17 p76/kr1/tkbo00/seg18 p77/kr0/tkbo01/seg19 p30/ti03/to03/remoout/seg20 p31/intp3/rtc1hz/seg21 p32/ti01/to01/seg22 p33/intp4/sck30/scl30/seg23 p34/si30/rxd3/sda30/seg24 p35/so30/txd3/seg25 p125/v l3 /(ti06)/(to06) v l4 v l2 v l1 p126/capl/(ti04)/(to04) p127/caph/(ti03)/(to03)/(remoout) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 123 456 78910 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p152/ani2 p151/ani1/av refm p150/ani0/av refp p130 p46/ano1 p45/ano0 p44/ivref0 p43/(intp7)/ivcmp0 p40/tool0/(ti00)/(to00) reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss0 v dd0 p60/scla0/(ti01)/(to01) p61/sdaa0/(ti02)/(to02) p12/txd2/so20/seg42 p00/sck10/scl10/seg48 p01/si10/rxd1/sda10/seg49 p02/so10/txd1/(pclbuz0)/seg50 p03/ti00/to00/intp1/seg51 p04/intp2/seg52 p05/ti02/to02/seg53 p06/intp5/seg54 p07/ti06/to06/seg55 com0 com1 com2 com3 com4/seg0 com5/seg1 com6/seg2 com7/seg3 p50/seg4/intp6 p51/seg5 p52/seg6
rl78/l1c 1. outline r01ds0192ej0200 rev. 2.00 page 7 of 149 feb 21, 2014 1.3.3 85-pin products (with usb) pin name pin name pin name pin name pin name a1 com7/seg3 c1 com2 e1 p04/intp2/seg52 g1 p00/sck10/scl10/ seg48 j1 v ss0 a2 p51/seg5 c2 com5/seg1 e2 p05/ti02/to02/seg53 g2 v ss0 j2 p11/rxd2/si20/sda20/ seg41/vcout0 a3 p70/kr7/seg12 c3 com6/seg2 e3 p06/intp5/seg54 g3 p12/txd2/so20/seg42/ vcout1 j3 p26/so00/txd0/ tooltxd/seg38 a4 p73/kr4/tkbo21/seg15 c4 p71/kr6/seg13 e4 ? g4 ? j4 p23/ti07/to07/seg35 a5 p74/kr3/tkbo10/seg16 c5 p76/kr1/tkbo00/seg18 e5 ? g5 ? j5 p20/ani20/seg32 a6 p31/intp3/rtc1hz/ seg21 c6 p77/kr0/tkbo01/seg19 e6 ? g6 ? j6 p141/ani17/seg29 a7 p33/intp4/sck30/scl30/ seg23 c7 p34/si30/rxd3/sda30/ seg24 e7 ? g7 ? j7 u regc a8 p35/so30/txd3/seg25 c8 v l1 e8 p40/tool0/(ti00)/(to00) g8 p44/(sck10)/(scl10)/ ivref0 j8 uv bus a9 v l4 c9 p61/sdaa0/(ti02)/(to02) e9 p137/intp0 g9 p45/ano0 j9 av dd a10 p126/capl/(ti04)/(to04) c10 v dd0 e10 p122/x2/exclk g10 p123/xt1 j10 p150/ani0/av refp b1 com4/seg0 d1 com0 f1 p03/ti00/to00/intp1/ seg51 h1 v ss0 k1 v ss0 b2 p50/seg4/intp6 d2 com1 f2 p02/so10/txd1/ (pclbuz0)/seg50 h2 v ss0 k2 p27/ti05/to05/(intp5)/ pclbuz1/seg39 b3 p52/seg6 d3 p07/ti06/to06/seg55 f3 p01/si10/rxd1/sda10/ seg49 h3 p10/intp7/pclbuz0/ sck20/scl20/seg40 k3 p25/si00/rxd0/ toolrxd/sda00/seg37 b4 p72/kr5/tkbo20/seg14 d4 com3 f4 ? h4 p24/sck00/scl00/ seg36 k4 p22/ti04/to04/seg34 b5 p75/kr2/tkbo11/seg17 d5 ? f5 ? h5 p21/ani21/seg33 k5 p143/ani19/seg31 b6 p30/ti03/to03/ remoout/seg20 d6 ? f6 ? h6 p140/ani16/seg28 k6 p142/ani18/seg30 b7 p32/ti01/to01/seg22 d7 ? f7 ? h7 p152/ani2 k7 udm b8 p125/v l3 /(ti06)/(to06) d8 p60/scla0/(ti01)/(to01) f8 p43/(intp7)/(si10)/ (rxd1)/(sda10)/ivcmp0 h8 p46/ano1 k8 udp b9 v l2 d9 regc f9 reset h9 p130 k9 av ss b10 p127/caph/(ti03)/ (to03)/(remoout) d10 p121/x1 f10 v ss0 h10 p124/xt2/exclks k10 p151/ani1/av refm a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 d10 d9 d8 d4 d3 d2 d1 e10 e9 e8 e3 e2 e1 f10 f9 f8 f3 f2 f1 g10 g9 g8 g3 g2 g1 h10 h9 h8 h7 h6 h5 h4 h3 h2 h1 j10 j9 j8 j7 j6 j5 j4 j3 j2 j1 k10 k9 k8 k7 k6 k5 k4 k3 k2 k1
rl78/l1c 1. outline r01ds0192ej0200 rev. 2.00 page 8 of 149 feb 21, 2014 1.3.4 85-pin products (without usb) pin name pin name pin name pin name pin name a1 com7/seg3 c1 com2 e1 p04/intp2/seg52 g1 p00/sck10/scl10/ seg48 j1 v ss0 a2 p51/seg5 c2 com5/seg1 e2 p05/ti02/to02/seg53 g2 v ss0 j2 p11/rxd2/si20/sda20/ seg41/vcout0 a3 p70/kr7/seg12 c3 com6/seg2 e3 p06/intp5/seg54 g3 p12/txd2/so20/seg42/ vcout1 j3 p26/so00/txd0/ tooltxd/seg38 a4 p73/kr4/tkbo21/seg15 c4 p71/kr6/seg13 e4 ? g4 ? j4 p23/ti07/to07/seg35 a5 p74/kr3/tkbo10/seg16 c5 p76/kr1/tkbo00/seg18 e5 ? g5 ? j5 p20/ani20/seg32 a6 p31/intp3/rtc1hz/ seg21 c6 p77/kr0/tkbo01/ seg19 e6 ? g6 ? j6 p141/ani17/seg29 a7 p33/intp4/sck30/ scl30/seg23 c7 p34/si30/rxd3/sda30/ seg24 e7 ? g7 ? j7 p82 a8 p35/so30/txd3/seg25 c8 v l1 e8 p40/tool0/(ti00)/(to00) g8 p44/(sck10)/(scl10)/ ivref0 j8 p83 a9 v l4 c9 p61/sdaa0/(ti02)/(to02) e9 p137/intp0 g9 p45/ano0 j9 av dd a10 p126/capl/(ti04)/(to04) c10 v dd0 e10 p122/x2/exclk g10 p123/xt1 j10 p150/ani0/av refp b1 com4/seg0 d1 com0 f1 p03/ti00/to00/intp1/ seg51 h1 v ss0 k1 v ss0 b2 p50/seg4/intp6 d2 com1 f2 p02/so10/txd1/ (pclbuz0)/seg50 h2 v ss0 k2 p27/ti05/to05/(intp5)/ pclbuz1/seg39 b3 p52/seg6 d3 p07/ti06/to06/seg55 f3 p01/si10/rxd1/sda10/ seg49 h3 p10/intp7/pclbuz0/ sck20/scl20/seg40 k3 p25/si00/rxd0/ toolrxd/sda00/seg37 b4 p72/kr5/tkbo20/seg14 d4 com3 f4 ? h4 p24/sck00/scl00/ seg36 k4 p22/ti04/to04/seg34 b5 p75/kr2/tkbo11/seg17 d5 ? f5 ? h5 p21/ani21/seg33 k5 p143/ani19/seg31 b6 p30/ti03/to03/ remoout/seg20 d6 ? f6 ? h6 p140/ani16/seg28 k6 p142/ani18/seg30 b7 p32/ti01/to01/seg22 d7 ? f7 ? h7 p152/ani2 k7 p156/ani6 b8 p125/v l3 /(ti06)/(to06) d8 p60/scla0/(ti01)/(to01) f8 p43/(intp7)/(si10)/ (rxd1)/(sda10)/ivcmp0 h8 p46/ano1 k8 p155/ani5 b9 v l2 d9 regc f9 reset h9 p130 k9 av ss b10 p127/caph/(ti03)/ (to03)/(remoout) d10 p121/x1 f10 v ss0 h10 p124/xt2/exclks k10 p151/ani1/av refm a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 d10 d9 d8 d4 d3 d2 d1 e10 e9 e8 e3 e2 e1 f10 f9 f8 f3 f2 f1 g10 g9 g8 g3 g2 g1 h10 h9 h8 h7 h6 h5 h4 h3 h2 h1 j10 j9 j8 j7 j6 j5 j4 j3 j2 j1 k10 k9 k8 k7 k6 k5 k4 k3 k2 k1
rl78/l1c 1. outline r01ds0192ej0200 rev. 2.00 page 9 of 149 feb 21, 2014 1.3.5 100-pin products (with usb) ? 100-pin plastic lfqfp (fine pitch) (14 ? 14 mm, 0.5 mm pitch) caution 1. connect the regc pin to v ss pin via a capacitor (0.47 to 1 ? f). caution 2. connect the u regc pin to v ss pin via a capacitor (0.33 ? f). remark 1. for pin identification, see 1.4 pin identification . remark 2. functions in parentheses in the above figure can be assi gned via settings in the peripher al i/o redirection register (pior). 1 2 3 4 5 6 7 8 9 1011121314151617181920 p153/ani3 p152/ani2 p151/ani1/av refm p150/ani0/av refp p130 p46/ano1 p45/ano0 p44/(sck10)/(scl10)/ivref0 p43/(intp7)/(si10)/(rxd1)/(sda10)/ivcmp0 p42/ti05/to05/(so10)/(txd1)/ivcmp1 p41/(ti07)/(to07)/ivref1 p40/tool0/(ti00)/(to00) reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss0 21 22 23 24 25 v dd0 p60/scla0/(ti01)/(to01) p61/sdaa0/(ti02)/(to02) p127/caph/(ti03)/(to03)/(remoout) p126/capl/(ti04)/(to04) p70/kr7/seg12 p71/kr6/seg13 p72/kr5/tkbo20/seg14 p73/kr4/tkbo21/seg15 p74/kr3/tkbo10/seg16 p75/kr2/tkbo11/seg17 p76/kr1/tkbo00/seg18 p77/kr0/tkbo01/seg19 p30/ti03/to03/remoout/seg20 p31/intp3/rtc1hz/seg21 p32/ti01/to01/seg22 p33/intp4/sck30/scl30/seg23 p34/si30/rxd3/sda30/seg24 p35/so30/txd3/seg25 p36/seg26 p37/seg27 p125/v l3 /(ti06)/(to06) v l4 v l2 v l1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 p12/txd2/so20/seg42/vcout1 p13/seg43 p14/seg44 p15/seg45 p16/seg46 p17/seg47 p00/sck10/scl10/seg48 p01/si10/rxd1/sda10/seg49 p02/so10/txd1/(pclbuz0)/seg50 p03/ti00/to00/intp1/seg51 p04/intp2/seg52 p05/ti02/to02/seg53 p06/intp5/seg54 p07/ti06/to06/seg55 com0 com1 com2 com3 com4/seg0 p23/ti07/to07/seg35 p22/ti04/to04/seg34 p21/ani21/seg33 p20/ani20/seg32 p143/ani19/seg31 p142/ani18/seg30 p141/ani17/seg29 p140/ani16/seg28 v dd1 v ss1 u regc uv bus udm udp p156/ani6 p155/ani5 av dd av ss p154/ani4 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 p24/sck00/scl00/seg36 81 p25/si00/rxd0/toolrxd/sda00/seg37 80 p26/so00/txd0/tooltxd/seg38 79 p27/(ti05)/(to05)/(intp5)/pclbuz1/seg39 78 p10/intp7/pclbuz0/sck20/scl20/seg40 77 p11/rxd2/si20/sda20/seg41/vcout0 76 56 com5/seg1 55 com6/seg2 54 com7/seg3 53 p50/seg4/intp6 52 p51/seg5 51 p52/seg6 p53/seg7 p54/seg8 p55/seg9 p56/seg10 p57/seg11
rl78/l1c 1. outline r01ds0192ej0200 rev. 2.00 page 10 of 149 feb 21, 2014 1.3.6 100-pin products (without usb) ? 100-pin plastic lfqfp (fine pitch) (14 ? 14 mm, 0.5 mm pitch) caution connect the regc pin to v ss pin via a capacitor (0.47 to 1 ? f). remark 1. for pin identification, see 1.4 pin identification . remark 2. functions in parentheses in the above figure can be assi gned via settings in the peripher al i/o redirection register (pior). 1 2 3 4 5 6 7 8 9 1011121314151617181920 p153/ani3 p152/ani2 p151/ani1/av refm p150/ani0/av refp p130 p46/ano1 p45/ano0 p44/(sck10)/(scl10)/ivref0 p43/(intp7)/(si10)/(rxd1)/(sda10)/ivcmp0 p42/ti05/to05/(so10)/(txd1)/ivcmp1 p41/(ti07)/(to07)/ivref1 p40/tool0/(ti00)/(to00) reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss0 21 22 23 24 25 v dd0 p60/scla0/(ti01)/(to01) p61/sdaa0/(ti02)/(to02) p127/caph/(ti03)/(to03)/(remoout) p126/capl/(ti04)/(to04) p70/kr7/seg12 p71/kr6/seg13 p72/kr5/tkbo20/seg14 p73/kr4/tkbo21/seg15 p74/kr3/tkbo10/seg16 p75/kr2/tkbo11/seg17 p76/kr1/tkbo00/seg18 p77/kr0/tkbo01/seg19 p30/ti03/to03/remoout/seg20 p31/intp3/rtc1hz/seg21 p32/ti01/to01/seg22 p33/intp4/sck30/scl30/seg23 p34/si30/rxd3/sda30/seg24 p35/so30/txd3/seg25 p36/seg26 p37/seg27 p125/v l3 /(ti06)/(to06) v l4 v l2 v l1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 p12/txd2/so20/seg42/vcout1 p13/seg43 p14/seg44 p15/seg45 p16/seg46 p17/seg47 p00/sck10/scl10/seg48 p01/si10/rxd1/sda10/seg49 p02/so10/txd1/(pclbuz0)/seg50 p03/ti00/to00/intp1/seg51 p04/intp2/seg52 p05/ti02/to02/seg53 p06/intp5/seg54 p07/ti06/to06/seg55 com0 com1 com2 com3 com4/seg0 p23/ti07/to07/seg35 p22/ti04/to04/seg34 p21/ani21/seg33 p20/ani20/seg32 p143/ani19/seg31 p142/ani18/seg30 p141/ani17/seg29 p140/ani16/seg28 v dd1 v ss1 p80 p81 p82 p83 p156/ani6 p155/ani5 av dd av ss p154/ani4 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 p24/sck00/scl00/seg36 81 p25/si00/rxd0/toolrxd/sda00/seg37 80 p26/so00/txd0/tooltxd/seg38 79 p27/(ti05)/(to05)/(intp5)/pclbuz1/seg39 78 p10/intp7/pclbuz0/sck20/scl20/seg40 77 p11/rxd2/si20/sda20/seg41/vcout0 76 56 com5/seg1 55 com6/seg2 54 com7/seg3 53 p50/seg4/intp6 52 p51/seg5 51 p52/seg6 p53/seg7 p54/seg8 p55/seg9 p56/seg10 p57/seg11
rl78/l1c 1. outline r01ds0192ej0200 rev. 2.00 page 11 of 149 feb 21, 2014 1.4 pin identification ani0 to ani6, : analog input scl00, scl10, scl20, scl30 : serial clock output ani16 to ani21 sdaa0, sda00, sda10, : serial data input/output ano0, ano1 : analog output sda20, sda30 av dd : analog power supply seg0 to seg55 : lcd segment output av refm : analog reference voltage si00, si10, si20, si30 : serial data input minus so00, so10, so20, so30 : serial data output av refp : analog reference voltage ti00 to ti07 : timer input plus to00 to to07 : timer output av ss : analog ground tkbo00, tkbo01, tkbo10, caph, capl : capacitor for lcd tkbo11, tkbo20, tkbo21 com0 to com7 : lcd common output tool0 : data input/output for tool exclk : external clock input toolrxd, tooltxd : data input/output for (main system cloc k) external device exclks : external clock input udm, udp : usb input/output (subsystem clock) u regc : usb regulator capacitance intp0 to intp7 : external interrupt input uv bus : usb input/usb power supply ivcmp0, ivcmp1 : comparator input txd0 to txd3 : transmit data ivref0, ivref1 : comparator reference input vcout0, vcout1 : comparator output kr0 to kr7 : key return v dd0 , v dd1 : power supply p00 to p07 : port 0 v l1 to v l4 : lcd power supply p10 to p17 : port 1 v ss0 , v ss1 : ground p20 to p27 : port 2 x1, x2 : crystal oscillator p30 to p37 : port 3 (main system clock) p40 to p46 : port 4 xt1, xt2 : crystal oscillator p50 to p57 : port 5 (subsystem clock) p60 to p62 : port 6 p70 to p77 : port 7 p80 to p83 : port 8 p121 to p127 : port 12 p130, p137 : port 13 p140 to p143 : port 14 p150 to p156 : port 15 pclbuz0, pclbuz1 : programmable clock output/ buzzer output regc : regulator capacitance remoout : remote control output reset :reset rtc1hz : real-time clock correction clock (1 hz) output rxd0 to rxd3 : receive data sck00, sck10, sck20, sck30 : serial clock input/output scla0 : serial clock input/output
rl78/l1c 1. outline r01ds0192ej0200 rev. 2.00 page 12 of 149 feb 21, 2014 1.5 block diagram 1.5.1 80/85-pin products (with usb) rtc1hz window watchdog timer low-speed on-chip oscillator 12- bit interval timer real-time clock buzzer output pclbuz0, pclbuz1 clock output control 2 data transfer control event link controller bcd adjustment crc sdaa0 scla0 serial interface iica0 ram usb voltage regulator u regc multiplier & divider, mulitiply- accumulator rl78 cpu core code flash memory data flash memory serial array unit1 (4 ch) rxd2 txd2 uart2 rxd3 txd3 uart3 sck20 so20 si20 csi20 sck30 so30 si30 csi30 scl20 sda20 iic20 scl30 sda30 iic30 usb uv bus udp udm port 2 p20 to p27 8 port 6 p60, p61 2 port 7 p70 to p77 8 port 12 p121 to p124 4 p125 to p127 3 p137 port 13 p130 port 14 p140 to p143 4 key return kr0 to kr7 8 power on reset/ voltage detector por/lvd control reset control tool0 on-chip debug system control high-speed on-chip oscillator pll voltage regulator regc interrupt control intp0 to intp7 8 ano0 d/a converter ano1 timer kb2_0 tkbo00 tkbo01 timer kb2_1 tkbo10 tkbo11 timer kb2_2 tkbo20 tkbo21 reset x1 x2/exclk xt1 xt2/exclks port 0 p00 to p07 8 timer array unit0 (8 ch) ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 remote carrier ti00/to00 ti01/to01 ti02/to02 ti03/to03 ti04/to04 ti05/to05 ti06/to06 ti07/to07 remoout lcd controller/ driver ram space for lcd data seg0 to seg6, seg12 to seg25, seg27 to seg42, seg48 to seg55 44 8 com0 to com7 v l1 to v l4 caph capl a/d converter ani2 ani16 to ani21 6 av refp /ani0 av refm /ani1 toolrxd, tooltxd av ss , v ss0 av dd , v dd0 port 1 p10 to p12 3 port 3 p30 to p35 6 port 4 p40, p43 to p46 5 port 5 p50 to p52 3 port 15 p150 to p152 3 comparator (1 ch) comparator0 ivcmp0 ivref0 vcout0 serial array unit0 (4 ch) uart0 linsel uart1 csi00 csi10 iic00 iic10 rxd0 txd0 rxd1 txd1 sck00 si00 so00 sck10 si10 so10 scl00 sda00 scl10 sda10
rl78/l1c 1. outline r01ds0192ej0200 rev. 2.00 page 13 of 149 feb 21, 2014 1.5.2 80/85-pin products (without usb) rtc1hz window watchdog timer low-speed on-chip oscillator 12- bit interval timer real-time clock buzzer output pclbuz0, pclbuz1 clock output control 2 data transfer control event link controller bcd adjustment crc sdaa0 scla0 serial interface iica0 ram multiplier & divider, mulitiply- accumulator rl78 cpu core code flash memory data flash memory serial array unit1 (4 ch) rxd2 txd2 uart2 rxd3 txd3 uart3 sck20 so20 si20 csi20 sck30 so30 si30 csi30 scl20 sda20 iic20 scl30 sda30 iic30 a/d converter 3 ani2, ani5, ani6 ani16 to ani21 6 av refp /ani0 av refm /ani1 port 2 p20 to p27 8 port 6 p60, p61 2 port 7 p70 to p77 8 timer kb2_0 tkbo00 tkbo01 timer kb2_1 tkbo10 tkbo11 timer kb2_2 tkbo20 tkbo21 serial array unit0 (4 ch) uart0 linsel uart1 csi00 csi10 iic00 iic10 rxd0 txd0 rxd1 txd1 sck00 si00 so00 sck10 si10 so10 scl00 sda00 scl10 sda10 port 0 p00 to p07 8 lcd controller/ driver ram space for lcd data seg0 to seg6, seg12 to seg25, seg27 to seg42, seg48 to seg55 44 8 com0 to com7 v l1 to v l4 caph capl toolrxd, tooltxd av ss , v ss0 av dd , v dd0 port 1 p10 to p12 3 port 3 p30 to p35 6 port 4 p40, p43 to p46 5 port 5 p50 to p52 3 port 12 p121 to p124 4 p125 to p127 3 p137 port 13 p130 port 14 p140 to p143 4 key return kr0 to kr7 8 power on reset/ voltage detector por/lvd control reset control tool0 on-chip debug voltage regulator regc interrupt control intp0 to intp7 8 ano0 d/a converter ano1 port 15 p150 to p152, p155, p156 5 system control high-speed on-chip oscillator reset x1 x2/exclk xt1 xt2/exclks comparator (1 ch) comparator0 ivcmp0 ivref0 vcout0 port 8 p82, p83 2 timer array unit0 (8 ch) ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 remote carrier ti00/to00 ti01/to01 ti02/to02 ti03/to03 ti04/to04 ti05/to05 ti06/to06 ti07/to07 remoout
rl78/l1c 1. outline r01ds0192ej0200 rev. 2.00 page 14 of 149 feb 21, 2014 1.5.3 100-pin products (with usb) rtc1hz window watchdog timer low-speed on-chip oscillator 12- bit interval timer real-time clock lcd controller/ driver ram space for lcd data seg0 to seg55 56 8 com0 to com7 v l1 to v l4 caph capl buzzer output pclbuz0, pclbuz1 clock output control 2 data transfer control event link controller bcd adjustment crc toolrxd, tooltxd av ss , v ss0 , v ss1 av dd , v dd0 , v dd1 sdaa0 scla0 serial interface iica0 ram usb voltage regulator u regc multiplier & divider, mulitiply- accumulator rl78 cpu core code flash memory data flash memory a/d converter 5 ani2 to ani6 ani16 to ani21 6 av refp /ani0 av refm /ani1 usb uv bus udp udm port 1 p10 to p17 8 port 2 p20 to p27 8 port 3 p30 to p37 8 port 4 p40 to p46 7 port 5 p50 to p57 8 port 6 p60, p61 2 port 7 p70 to p77 8 port 12 p121 to p124 4 p125 to p127 3 p137 port 13 p130 port 14 p140 to p143 4 port 15 p150 to p156 7 key return kr0 to kr7 8 power on reset/ voltage detector por/lvd control reset control tool0 on-chip debug system control high-speed on-chip oscillator pll voltage regulator regc interrupt control intp0 to intp7 8 ano0 d/a converter ano1 timer kb2_0 tkbo00 tkbo01 timer kb2_1 tkbo10 tkbo11 timer kb2_2 tkbo20 tkbo21 serial array unit0 (4 ch) uart0 linsel uart1 csi00 csi10 iic00 iic10 rxd0 txd0 rxd1 txd1 sck00 si00 so00 sck10 si10 so10 scl00 sda00 scl10 sda10 reset x1 x2/exclk xt1 xt2/exclks port 0 p00 to p07 8 timer array unit0 (8 ch) ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 remote carrier ti00/to00 ti01/to01 ti02/to02 ti03/to03 ti04/to04 ti05/to05 ti06/to06 ti07/to07 remoout serial array unit1 (4 ch) rxd2 txd2 uart2 rxd3 txd3 uart3 sck20 so20 si20 csi20 sck30 so30 si30 csi30 scl20 sda20 iic20 scl30 sda30 iic30 comparator (2 ch) comparator0 ivcmp0 ivref0 vcout0 comparator1 ivcmp1 ivref1 vcout1
rl78/l1c 1. outline r01ds0192ej0200 rev. 2.00 page 15 of 149 feb 21, 2014 1.5.4 100-pin products (without usb) rtc1hz window watchdog timer low-speed on-chip oscillator 12- bit interval timer real-time clock lcd controller/ driver ram space for lcd data seg0 to seg55 56 8 com0 to com7 v l1 to v l4 caph capl buzzer output pclbuz0, pclbuz1 clock output control 2 data transfer control event link controller bcd adjustment crc toolrxd, tooltxd av ss , v ss0 , v ss1 av dd , v dd0 , v dd1 sdaa0 scla0 serial interface iica0 ram multiplier & divider, mulitiply- accumulator rl78 cpu core code flash memory data flash memory a/d converter 5 ani2 to ani6 ani16 to ani21 6 av refp /ani0 av refm /ani1 port 1 p10 to p17 8 port 2 p20 to p27 8 port 3 p30 to p37 8 port 4 p40 to p46 7 port 5 p50 to p57 8 port 6 p60, p61 2 timer kb2_0 tkbo00 tkbo01 timer kb2_1 tkbo10 tkbo11 timer kb2_2 tkbo20 tkbo21 serial array unit0 (4 ch) uart0 linsel uart1 csi00 csi10 iic00 iic10 rxd0 txd0 rxd1 txd1 sck00 si00 so00 sck10 si10 so10 scl00 sda00 scl10 sda10 port 0 p00 to p07 8 port 7 p70 to p77 8 port 12 p121 to p124 4 p125 to p127 3 p137 port 13 p130 port 14 p140 to p143 4 port 15 p150 to p156 7 key return kr0 to kr7 8 power on reset/ voltage detector por/lvd control reset control tool0 on-chip debug voltage regulator regc interrupt control intp0 to intp7 8 ano0 d/a converter ano1 system control high-speed on-chip oscillator reset x1 x2/exclk xt1 xt2/exclks comparator (2 ch) comparator0 ivcmp0 ivref0 vcout0 comparator1 ivcmp1 ivref1 vcout1 timer array unit0 (8 ch) ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 remote carrier ti00/to00 ti01/to01 ti02/to02 ti03/to03 ti04/to04 ti05/to05 ti06/to06 ti07/to07 remoout serial array unit1 (4 ch) rxd2 txd2 uart2 rxd3 txd3 uart3 sck20 so20 si20 csi20 sck30 so30 si30 csi30 scl20 sda20 iic20 scl30 sda30 iic30 port 8 p80 to p83 4
rl78/l1c 1. outline r01ds0192ej0200 rev. 2.00 page 16 of 149 feb 21, 2014 1.6 outline of functions note 1. in the case of the 16 kb, this is about 15 kb when the self-programming function and data flash function are used. note 2. in the pll clock 48 mhz operation, the system clock is 2/ 4/8 dividing ratio. note 3. the number of outputs varies, depending on the setting of channels in use and the number of the master. [80/85-pin, 100-pin products (with usb)] (1/2) item 80/85-pin 100-pin r5f110mx/r5f110nx (x = e to h, j) r5f110px (x = e to h, j) code flash memory (kb) 64 to 256 64 to 256 data flash memory (kb) 8 8 ram (kb) 8 to 16 note 1 8 to 16 note 1 memory space 1 mb main system clock high-speed system clock x1 (crystal/ceramic) oscillation, external main system clock input (exclk) 1 to 20 mhz: v dd = 2.7 to 3.6 v, 1 to 8 mhz: v dd = 1.8 to 2.7 v, 1 to 4 mhz: v dd = 1.6 to 1.8 v high-speed on-chip oscillator clock hs (high-speed main) operation mode: 1 to 24 mhz (v dd = 2.7 to 3.6 v), hs (high-speed main) operation mode: 1 to 16 mhz (v dd = 2.4 to 3.6 v), ls (low-speed main) operation mode: 1 to 8 mhz (v dd = 1.8 to 3.6 v), lv (low-voltage main) operation mode: 1 to 4 mhz (v dd = 1.6 to 3.6 v) pll clock 6, 12, 24 mhz note 2 : v dd = 2.4 to 3.6 v subsystem clock xt1 (crystal) oscillation, external subsystem clock input (exclks) 32.768 khz (typ.): v dd = 1.6 to 3.6 v low-speed on-chip oscillator clock 15 khz (typ.): v dd = 1.6 to 3.6 v general-purpose register 8 bits ? 32 registers (8 bits ? 8 registers ? 4 banks) minimum instruction execution time 0.04167 ? s (high-speed on-chip oscillator clock: f hoco = f ih = 24 mhz operation) 0.04167 ? s (pll clock: f pll = 48 mhz/f ih = 24 mhz note 2 operation) 0.05 ? s (high-speed system clock: f mx = 20 mhz operation) 30.5 ? s (subsystem clock: f sub = 32.768 khz operation) instruction set ? data transfer (8/16 bits) ? adder and subtractor/logical operation (8/16 bits) ? multiplication (8 bits ? 8 bits, 16 bits ? 16 bits), division (16 bits ? 16 bits, 32 bits ? 32 bits) ? multiplication and accumulation (16 bits ? 16 bits + 32 bits) ? rotate, barrel shift, and bit manipulation (set, reset, test, and boolean operation), etc. i/o port total 59 77 cmos i/o 51 69 cmos input 55 cmos output 11 n-ch open-drain i/o (6 v tolerance) 22 timer 16-bit timer tau 8 channels (with 1 channel remote control output function) (timer outputs: 8, pwm outputs: 7 note 3 ) 16-bit timer kb2 3 channels (pwm outputs: 6) watchdog timer 1 channel 12-bit interval timer 1 channel real-time clock 2 1 channel rtc output 1 1 hz (subsystem clock: f sub = 32.768 khz)
rl78/l1c 1. outline r01ds0192ej0200 rev. 2.00 page 17 of 149 feb 21, 2014 note 1. the number in parentheses indicates the number of signal outputs when 8 coms are used. note 2. the illegal instruction is generated when instruction code ffh is executed. reset by the illegal instruction executi on not is issued by emulation with t he in-circuit emulator or on-chip debug emulator. (2/2) item 80/85-pin 100-pin r5f110mx/r5f110nx (x = e to h, j) r5f110px (x = e to h, j) clock output/buzzer output 2 2 ? 2.44 khz, 4.88 khz, 9.76 khz, 1.25 mhz, 2.5 mhz, 5 mhz, 10 mhz (main system clock: f main = 20 mhz operation) ? 256 hz, 512 hz, 1.024 khz, 2.048 khz, 4.096 khz, 8.192 khz, 16.384 khz, 32.768 khz (subsystem clock: f sub = 32.768 khz operation) 8/12-bit resolution a/d converter 9 channels 13 channels d/a converter 2 channels 2 channels comparator 1 channel 2 channels serial interface ? csi: 1 channel/uart (uart supporting lin-bus): 1 channel/simplified i 2 c: 1 channel ? csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel ? csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel ? csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel i 2 c bus 1 channel 1 channel usb function 1 channel lcd controller/driver internal voltage boosting method, capaci tor split method, and external resistance division method are switchable. segment signal output 44 (40) note 1 56 (52) note 1 common signal output 4 (8) note 1 data transfer controller (dtc) 32 sources 33 sources event link controller (elc) event input: 30, event trigger output: 22 event input: 31, event trigger output: 22 vectored interrupt sources internal 36 37 external 9 9 key interrupt 8 8 reset ? reset by reset pin ? internal reset by watchdog timer ? internal reset by power-on-reset ? internal reset by voltage detector ? internal reset by illegal instruction execution note 2 ? internal reset by ram parity error ? internal reset by illegal-memory access power-on-reset circuit ? power-on-reset: 1.51 ? 0.03 v ? power-down-reset: 1.50 ? 0.03 v voltage detector ? rising edge: 1.67 v to 3.13 v (12 stages) ? falling edge: 1.63 v to 3.06 v (12 stages) on-chip debug function provided power supply voltage v dd = 1.6 to 3.6 v operating ambient temperature t a = -40 to +85 ? c (a: consumer applications), t a = -40 to +105 c (g: industrial applications)
rl78/l1c 1. outline r01ds0192ej0200 rev. 2.00 page 18 of 149 feb 21, 2014 note 1. in the case of the 16 kb, this is about 15 kb when the self-programming function and data flash function are used. note 2. the number of outputs varies, depending on the setting of channels in use and the number of the master. [80/85-pin, 100-pin products (without usb)] (1/2) item 80/85-pin 100-pin r5f111mx/r5f111nx (x = e to h, j) r5f111px (x = e to h, j) code flash memory (kb) 64 to 256 64 to 256 data flash memory (kb) 8 8 ram (kb) 8 to 16 note 1 8 to 16 note 1 memory space 1 mb main system clock high-speed system clock x1 (crystal/ceramic) oscillation, external main system clock input (exclk) 1 to 20 mhz: v dd = 2.7 to 3.6 v, 1 to 8 mhz: v dd = 1.8 to 2.7 v, 1 to 4 mhz: v dd = 1.6 to 1.8 v high-speed on-chip oscillator clock hs (high-speed main) operation mode: 1 to 24 mhz (v dd = 2.7 to 3.6 v), hs (high-speed main) operation mode: 1 to 16 mhz (v dd = 2.4 to 3.6 v, ls (low-speed main) operation mode: 1 to 8 mhz (v dd = 1.8 to 3.6 v), lv (low-voltage main) operation mode: 1 to 4 mhz (v dd = 1.6 to 3.6 v) subsystem clock xt1 (crystal) oscillation, external subsystem clock input (exclks) 32.768 khz (typ.): v dd = 1.6 to 3.6 v low-speed on-chip oscillator clock 15 khz (typ.): v dd = 1.6 to 3.6 v general-purpose register 8 bits ? 32 registers (8 bits ? 8 registers ? 4 banks) minimum instruction execution time 0.04167 ? s (high-speed on-chip oscillator clock: f hoco = f ih = 24 mhz operation) 0.05 ? s (high-speed system clock: f mx = 20 mhz operation) 30.5 ? s (subsystem clock: f sub = 32.768 khz operation) instruction set ? data transfer (8/16 bits) ? adder and subtractor/logical operation (8/16 bits) ? multiplication (8 bits ? 8 bits, 16 bits ? 16 bits), division (16 bits ? 16 bits, 32 bits ? 32 bits) ? multiplication and accumulation (16 bits ? 16 bits + 32 bits) ? rotate, barrel shift, and bit manipulation (set, reset, test, and boolean operation), etc. i/o port total 63 81 cmos i/o 55 73 cmos input 55 cmos output 11 n-ch open-drain i/o (6 v tolerance) 22 timer 16-bit timer tau 8 channels (with 1 channel remote control output function) (timer outputs: 8, pwm outputs: 7 note 2 ) 16-bit timer kb2 3 channels (pwm outputs: 6) watchdog timer 1 channel 12-bit interval timer 1 channel real-time clock 2 1 channel rtc output 1 1 hz (subsystem clock: f sub = 32.768 khz)
rl78/l1c 1. outline r01ds0192ej0200 rev. 2.00 page 19 of 149 feb 21, 2014 note 1. the number in parentheses indicates the number of signal outputs when 8 coms are used. note 2. the illegal instruction is generated when instruction code ffh is executed. reset by the illegal instruction executi on not is issued by emulation with t he in-circuit emulator or on-chip debug emulator. (2/2) item 80/85-pin 100-pin r5f111mx/r5f111nx (x = e to h, j) r5f111px (x = e to h, j) clock output/buzzer output 2 2 ? 2.44 khz, 4.88 khz, 9.76 khz, 1.25 mhz, 2.5 mhz, 5 mhz, 10 mhz (main system clock: f main = 20 mhz operation) ? 256 hz, 512 hz, 1.024 khz, 2.048 khz, 4.096 khz, 8.192 khz, 16.384 khz, 32.768 khz (subsystem clock: f sub = 32.768 khz operation) 8/12-bit resolution a/d converter 11 channels 13 channels d/a converter 2 channels 2 channels comparator 1 channel 2 channels serial interface ? csi: 1 channel/uart (uart supporting lin-bus): 1 channel/simplified i 2 c: 1 channel ? csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel ? csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel ? csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel i 2 c bus 1 channel 1 channel lcd controller/driver internal voltage boosting method, capaci tor split method, and external resistance division method are switchable. segment signal output 44 (40) note 1 56 (52) note 1 common signal output 4 (8) note 1 data transfer controller (dtc) 30 sources 31 sources event link controller (elc) event input: 30, event trigger output: 22 event input: 31, event trigger output: 22 vectored interrupt sources internal 32 33 external 9 9 key interrupt 8 8 reset ? reset by reset pin ? internal reset by watchdog timer ? internal reset by power-on-reset ? internal reset by voltage detector ? internal reset by illegal instruction execution note 2 ? internal reset by ram parity error ? internal reset by illegal-memory access power-on-reset circuit ? power-on-reset: 1.51 ? 0.03 v ? power-down-reset: 1.50 ? 0.03 v voltage detector ? rising edge: 1.67 v to 3.13 v (12 stages) ? falling edge: 1.63 v to 3.06 v (12 stages) on-chip debug function provided power supply voltage v dd = 1.6 to 3.6 v operating ambient temperature t a = -40 to +85 ? c (a: consumer applications), t a = -40 to +105 ? c (g: industrial applications)
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 20 of 149 feb 21, 2014 2. electrical spec ifications (a: t a = -40 to +85 c) this chapter describes the electrical specificatio ns for the products a: consumer applications (t a = -40 to +85 c) and g: industrial applications (when used in the range of t a = -40 to +85 c). caution 1. the rl78 microcontroller has an on-chip debug function, which is provided for development and evaluation. do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. caution 2. the pins mounted depend on the product. refer to 1.3.1 80-pin products (with usb) to 1.3.6 100-pin products (without usb).
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 21 of 149 feb 21, 2014 2.1 absolute maximum ratings note 1. connect the regc pin to v ss via a capacitor (0.47 to 1 ? f). this value regulates the absolute maximum rating of the regc pin. do not use this pin with voltage applied to it. note 2. connect the u regc pin to vss via a capacitor (0.33 ? f). this value regulates the absolute maximum rating of the u regc pin. do not use this pin with voltage applied to it. note 3. must be 6.5 v or lower. note 4. must be 4.6 v or lower. note 5. do not exceed av ref(+) + 0.3 v in case of a/d conversion target pin. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark 1. unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. remark 2. av ref (+) : + side reference voltage of the a/d converter. remark 3. v ss : reference voltage absolute maximum ratings (t a = 25 ?c) (1/3) parameter symbols conditions ratings unit supply voltage v dd -0.5 to + 6.5 v uv bus -0.5 to + 6.5 v av dd av dd ? ? v dd -0.5 to + 4.6 v regc pin input voltage v iregc regc -0.3 to + 2.8 and -0.3 to v dd + 0.3 note 1 v u regc pin input voltage v iuregc u regc -0.3 to uv bus + 0.3 note 2 v input voltage v i1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p46, p50 to p57, p70 to p77, p80 to p83, p125 to p127, p137, p140 to p143, exclk, exclks, reset -0.3 to v dd + 0.3 note 3 v v i2 p60, p61 (n-ch open-drain) -0.3 to + 6.5 v v i3 udp, udm -0.3 to + 6.5 v v i4 p150 to p156 -0.3 to av dd + 0.3 note 4 v output voltage v o1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p46, p50 to p57, p60, p61, p70 to p77, p80 to p83, p125 to p127, p140 to p143 -0.3 to v dd + 0.3 note 3 v v o2 p130, p150 to p156 -0.3 to av dd + 0.3 note 3 v v o3 udp, udm -0.3 to + 3.8 v analog input voltage v ai1 ani16 to ani21 -0.3 to v dd + 0.3 and av ref(+) + 0.3 notes 3, 5 v v ai2 ani0 to ani6 -0.3 to av dd + 0.3 and av ref(+) + 0.3 notes 3, 5 v
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 22 of 149 feb 21, 2014 note 1. this value only indicates the absolute maxi mum ratings when applying voltage to the v l1 , v l2 , v l3 , and v l4 pins; it does not mean that applying voltage to these pins is recommen ded. when using the internal voltage boosting method or capacitance split method, connect these pins to v ss via a capacitor (0.47 ? 30%) and connect a capacitor (0.47 ? 30%) between the capl and caph pins. note 2. must be 6.5 v or lower. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. absolute maximum ratings (t a = 25 ?c) (2/3) parameter symbols conditions ratings unit lcd voltage v li1 v l1 input voltage note 1 -0.3 to +2.8 v v li2 v l2 input voltage note 1 -0.3 to +6.5 v v li3 v l3 input voltage note 1 -0.3 to +6.5 v v li4 v l4 input voltage note 1 -0.3 to +6.5 v v li5 capl, caph input voltage note 1 -0.3 to +6.5 v v lo1 v l1 output voltage -0.3 to +2.8 v v lo2 v l2 output voltage -0.3 to +6.5 v v lo3 v l3 output voltage -0.3 to +6.5 v v lo4 v l4 output voltage -0.3 to +6.5 v v lo5 capl, caph output voltage -0.3 to +6.5 v v lo6 com0 to com7 seg0 to seg55 output voltage external resistance division method -0.3 to v dd + 0.3 note 2 v capacitor split method -0.3 to v dd + 0.3 note 2 v internal voltage boosting method -0.3 to v li4 + 0.3 note 2 v
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 23 of 149 feb 21, 2014 caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. absolute maximum ratings (t a = 25 ?c) (3/3) parameter symbols conditions ratings unit output current, high i oh1 per pin p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p46, p50 to p57, p70 to p77, p80 to p83, p125 to p127, p140 to p143 -40 ma total of all pins -170 ma p40 to p46 -70 ma p00 to p07, p10 to p17, p20 to p27, p30 to p37, p50 to p57, p70 to p77, p80 to p83, p125 to p127, p140 to p143 -100 ma i oh2 per pin p130, p150 to p156 -0.1 ma total of all pins -0.8 ma i oh3 per pin udp, udm -3 ma output current, low i ol1 per pin p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p46, p50 to p57, p60, p61, p70 to p77, p80 to p83, p125 to p127, p140 to p143 40 ma total of all pins 170 ma p40 to p46 70 ma p00 to p07, p10 to p17, p20 to p27, p30 to p37, p50 to p57, p70 to p77, p80 to p83, p125 to p127, p140 to p143 100 ma i ol2 per pin p130, p150 to p156 0.4 ma total of all pins 3.2 ma i ol3 per pin udp, udm 3 ma operating ambient temperature t a in normal operation mode -40 to +85 ? c in flash memory programming mode storage temperature t stg -65 to +150 ? c
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 24 of 149 feb 21, 2014 2.2 oscillator characteristics 2.2.1 x1 and xt1 oscill ator characteristics note indicates only permissible oscillat or frequency ranges. refer to ac characteristics for instruction execution time. request evaluation by the manufacturer of the oscilla tor circuit mounted on a boa rd to check the oscillator characteristics. caution since the cpu is started by the high-speed on-chip oscillator clock after a reset release, check the x1 clock oscillation stabilization time using the oscillation stabilization time counter status register (ostc) by the user. determine the oscillation stabilization time of the ostc register and the oscillation stabilization time select register (osts) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. remark when using the x1 and xt1 oscillator, refer to 5.4 system clock oscillator in the rl78/l1c user?s manual. (t a = -40 to +85 c, 1.6 v ? v dd ? 3.6 v, v ss = 0 v) parameter resonator conditions min. typ. max. unit x1 clock oscillation frequency (f x ) note ceramic resonator/crystal resonator 2.7 v ? ? v dd ? ? 3.6 v 1.0 20.0 mhz 2.4 v ? ? v dd < 2.7 v 1.0 16.0 1.8 v ? ? v dd < 2.4 v 1.0 8.0 1.6 v ? ? v dd < 1.8 v 1.0 4.0 xt1 clock oscillation frequency (f xt ) note crystal resonator 32 32.768 35 khz
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 25 of 149 feb 21, 2014 2.2.2 on-chip oscillator characteristics note 1. high-speed on-chip oscillator fr equency is selected with bits 0 to 4 of the opt ion byte (000c2h) and bits 0 to 2 of the hocodiv register. note 2. this only indicates t he oscillator characte ristics. refer to ac characteristics for instruction execution time. 2.2.3 pll oscillator characteristics note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. (t a = -40 to +85 c, 1.6 v ? v dd ? 3.6 v, v ss = 0 v) oscillators parameters conditions min. typ. max. unit high-speed on-chip oscillator clock frequency notes 1, 2 f hoco 14 8m h z high-speed on-chip oscillator clock frequency accuracy -20 to +85 ? c 1.8 v ? v dd ? 3.6 v -1.0 +1.0 % 1.6 v ? v dd ? 1.8 v -5.0 +5.0 % -40 to -20 ? c 1.8 v ? v dd < 3.6 v -1.5 +1.5 % 1.6 v ? v dd ? 1.8 v -5.5 +5.5 % low-speed on-chip oscillator clock frequency f il 15 khz low-speed on-chip oscillator clock frequency accuracy -15 +15 % (t a = -40 to +85 c, 2.4 v ? v dd ? 3.6 v, v ss = 0 v) oscillators parameters conditions min. typ. max. unit pll input frequency note f pllin high-speed system clock 6.00 16.00 mhz pll output frequency note f pll 48.00 mhz
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 26 of 149 feb 21, 2014 2.3 dc characteristics 2.3.1 pin characteristics note 1. value of current at which the device operation is guaranteed even if the current flows from the v dd pin to an output pin. note 2. however, do not exceed the total current value. note 3. specification under conditions where the duty factor is 70%. the output current value that has changed the duty ratio c an be calculated with the following expression (when changing the duty factor from 70% to n%). ? total output current of pins = (i oh ? 0.7)/(n ? 0.01) where n = 50% and i oh = -10.0 ma total output current of pins = (-10.0 ? 0.7)/(50 ? 0.01) = -14.0 ma however, the current that is allowed to flow into one pi n does not vary depending on the duty factor. a current higher than the absolute maximum rating must not flow into one pin. caution p00 to p02, p10 to p12, p24 to p26, p33 to p35, and p42 to p44 do not output high level in n-ch open-drain mode. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (t a = -40 to +85 c, 1.6 v ? av dd = v dd ? 3.6 v, v ss = 0 v) items symbol conditions min. typ. max. unit output current, high note 1 i oh1 per pin for p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p46, p50 to p57, p70 to p77, p80 to p83, p125 to p127, p140 to p143 -10.0 note 2 ma total of p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p46, p50 to p57, p70 to p77, p80 to p83, p125 to p127, p140 to p143 (when duty = 70% note 3 ) 2.7 v ? v dd ? 3.6 v -15.0 ma 1.8 v ? v dd < 2.7 v -7.0 ma 1.6 v ? v dd < 1.8 v -3 ma i oh2 per pin for p130, p150 to p156 1.6 v ? v dd ? 3.6 v -0.1 note 2 ma total of all pins 1.6 v ? v dd ? 3.6 v -0.8 ma
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 27 of 149 feb 21, 2014 note 1. value of current at which the device operation is guaranteed even if the current flows from an output pin to the v ss pin. note 2. however, do not exceed the total current value. note 3. specification under conditions where the duty factor is 70%. the output current value that has changed the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). ? total output current of pins = (i ol ? 0.7)/(n ? 0.01) where n = 50% and i ol = 10.0 ma total output current of pins = (10.0 ? 0.7)/(50 ? 0.01) = 14.0 ma however, the current that is allowed to flow in to one pin does not vary depending on the duty factor. a current higher than the absolute maximum rating must not flow into one pin. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (t a = -40 to +85 c, 1.6 v ? av dd = v dd ? 3.6 v, v ss = 0 v) items symbol conditions min. typ. max. unit output current, low note 1 i ol1 per pin for p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p46, p50 to p57, p60, p61, p70 to p77, p80 to p83, p125 to p127, p140 to p143 20.0 note 2 ma per pin for p60 and p61 15.0 note 2 ma total of p40 to p46 (when duty = 70% note 3 ) 2.7 v ? v dd ? 3.6 v 15.0 ma 1.8 v ? v dd < 2.7 v 9.0 ma 1.6 v ? v dd < 1.8 v 4.5 ma total of p00 to p07, p10 to p17, p20 to p27, p30 to p37, p50 to p57, p60, p61, p70 to p77, p80 to p83, p125 to p127, p140 to p143 (when duty = 70% note 3 ) 2.7 v ? v dd ? 3.6 v 35.0 ma 1.8 v ? v dd < 2.7 v 20.0 ma 1.6 v ? v dd < 1.8 v 10.0 ma total of all pins (when duty = 70% note 3 ) 50.0 ma i ol2 per pin for p130, p150 to p156 0.4 note 2 ma total of all pins 1.6 v ? v dd ? 3.6 v 3.2 ma
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 28 of 149 feb 21, 2014 caution the maximum value of v ih of pins p00 to p02, p10 to p12, p24 to p26, p33 to p35, and p42 to p44 is v dd , even in the n-ch open-drain mode. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (t a = -40 to +85 c, 1.6 v ? av dd = v dd ? 3.6 v, v ss = 0 v) items symbol conditions min. typ. max. unit input voltage, high v ih1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p46, p50 to p57, p70 to p77, p80 to p83, p125 to p127, p140 to p143 normal input buffer 0.8 v dd v dd v v ih2 p00, p01, p10, p11, p24, p25, p33, p34, p43, p44 ttl input buffer 3.3 v ? v dd ? 3.6 v 2.0 v dd v ttl input buffer 1.6 v ? v dd < 3.3 v 1.50 v dd v v ih3 p150 to p156 0.7 av dd av dd v v ih4 p60, p61 0.7 v dd 6.0 v v ih5 p121 to p124, p137, exclk, exclks, reset 0.8 v dd v dd v input voltage, low v il1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p46, p50 to p57, p70 to p77, p80 to p83, p125 to p127, p140 to p143 normal input buffer 0 0.2 v dd v v il2 p00, p01, p10, p11, p24, p25, p33, p34, p43, p44 ttl input buffer 3.3 v ? v dd ? 3.6 v 00.5v ttl input buffer 1.6 v ? v dd < 3.3 v 00.32v v il3 p150 to p156 0 0.3 av dd v v il4 p60, p61 0 0.3 v dd v v il5 p121 to p124, p137, exclk, exclks, reset 0 0.2 v dd v
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 29 of 149 feb 21, 2014 caution p00 to p02, p10 to p12, p24 to p26, p33 to p35, and p42 to p44 do not output high level in n-ch open-drain mode. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (t a = -40 to +85 c, 1.6 v ? av dd = v dd ? 3.6 v, v ss = 0 v) items symbol conditions min. typ. max. unit output voltage, high v oh1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p46, p50 to p57, p70 to p77, p80 to p83, p125 to p127, p140 to p143 2.7 v ? v dd ? 3.6 v, i oh1 = -2.0 ma v dd - 0.6 v 1.8 v ? v dd ? 3.6 v, i oh1 = -1.5 ma v dd - 0.5 v 1.6 v ? v dd < 3.6 v, i oh1 = -1.0 ma v dd - 0.5 v v oh2 p130, p150 to p156 1.6 v ? v dd ? 3.6 v, i oh2 = -100 ? a av dd - 0.5 v output voltage, low v ol1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p46, p50 to p57, p70 to p77, p80 to p83, p125 to p127, p140 to p143 2.7 v ? v dd ? 3.6 v, i ol1 = 3.0 ma 0.6 v 2.7 v ? v dd ? 3.6 v, i ol1 = 1.5 ma 0.4 v 1.8 v ? v dd ? 3.6 v, i ol1 = 0.6 ma 0.4 v 1.6 v ? v dd < 1.8 v, i ol1 = 0.3 ma 0.4 v v ol2 p130, p150 to p156 1.6 v ? v dd ? 3.6 v, i ol2 = 400 ? a 0.4 v v ol3 p60, p61 2.7 v ? v dd ? 3.6 v, i ol3 = 3.0 ma 0.4 v 1.8 v ? v dd ? 3.6 v, i ol3 = 2.0 ma 0.4 v 1.6 v ? v dd ? 1.8 v, i ol3 = 1.0 ma 0.4 v
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 30 of 149 feb 21, 2014 remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (t a = -40 to +85 c, 1.6 v ? av dd = v dd ? 3.6 v, v ss = 0 v) items symbol conditions min. typ. max. unit input leakage current, high i lih1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p46, p50 to p57, p60, p61, p70 to p77, p80 to p83, p125 to p127, p137, p140 to p143, reset v i = v dd 1 ? a i lih2 p20, p21, p140 to p143 v i = v dd 1 ? a i lih3 p121 to p124 (x1, x2, exclk, xt1, xt2, exclks) v i = v dd in input port or external clock input 1 ? a in resonator connection 10 ? a i lih4 p150 to p156 v i = av dd 1 ? a input leakage current, low i lil1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p46, p50 to p57, p60, p61, p70 to p77, p80 to p83, p125 to p127, p137, p140 to p143, reset v i = v ss -1 ? a i lil2 p20, p21, p140 to p143 v i = v ss -1 ? a i lil3 p121 to p124 (x1, x2, exclk, xt1, xt2, exclks) v i = v ss in input port or external clock input -1 ? a in resonator connection -10 ? a i lil4 p150 to p156 v i = av ss -1 ? a on-chip pull-up resistance r u1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p50 to p57, p70 to p77, p140 to p143, p125 to p127 v i = v ss 2.4 v ? v dd ? 3.6 v 10 20 100 k ? 1.6 v ? v dd ? 2.4 v 10 30 100 r u2 p40 to p46, p80 to p83 v i = v ss 10 20 100 k ?
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 31 of 149 feb 21, 2014 2.3.2 supply current characteristics (notes and remarks are listed on the next page.) (t a = -40 to +85 c, 1.6 v ? v dd ? 3.6 v, v ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit supply current note 1 i dd1 operating mode hs (high-speed main) mode note 5 f hoco = 48 mhz note 3 , f ih = 24 mhz note 3 basic operation v dd = 3.6 v 2.2 2.8 ma v dd = 3.0 v 2.2 2.8 normal operation v dd = 3.6 v 4.4 8.5 v dd = 3.0 v 4.4 8.5 f hoco = 24 mhz note 3 , f ih = 24 mhz note 3 basic operation v dd = 3.6 v 2.0 2.6 v dd = 3.0 v 2.0 2.6 normal operation v dd = 3.6 v 4.2 6.8 v dd = 3.0 v 4.2 6.8 f hoco = 16 mhz note 3 , f ih = 16 mhz note 3 normal operation v dd = 3.6 v 3.1 4.9 v dd = 3.0 v 3.1 4.9 ls (low-speed main) mode note 5 f hoco = 8 mhz note 3 , f ih = 8 mhz note 3 normal operation v dd = 3.0 v 1.4 2.2 ma v dd = 2.0 v 1.4 2.2 lv (low-voltage main) mode note 5 f hoco = 4 mhz note 3 , f ih = 4 mhz note 3 normal operation v dd = 3.0 v 1.3 1.8 ma v dd = 2.0 v 1.3 1.8 hs (high-speed main) mode note 5 f mx = 20 mhz note 2 , v dd = 3.6 v normal operation square wave input 3.5 5.5 ma resonator connection 3.6 5.7 f mx = 20 mhz note 2 , v dd = 3.0 v normal operation square wave input 3.5 5.5 resonator connection 3.6 5.7 f mx = 16 mhz note 2 , v dd = 3.6 v normal operation square wave input 2.9 4.5 resonator connection 3.1 4.6 f mx = 16 mhz note 2 , v dd = 3.0 v normal operation square wave input 2.9 4.5 resonator connection 3.1 4.6 f mx = 10 mhz note 2 , v dd = 3.6 v normal operation square wave input 2.1 3.2 resonator connection 2.2 3.2 f mx = 10 mhz note 2 , v dd = 3.0 v normal operation square wave input 2.1 3.2 resonator connection 2.2 3.2 ls (low-speed main) mode note 5 f mx = 8 mhz note 2 , v dd = 3.6 v normal operation square wave input 1.2 2.0 ma resonator connection 1.3 2.0 f mx = 8 mhz note 2 , v dd = 3.0 v normal operation square wave input 1.2 2.1 resonator connection 1.3 2.2 hs (high-speed main) mode (pll operation) f pll = 48 mhz, f clk = 24 mhz note 2 normal operation v dd = 3.6 v 4.7 7.5 ma v dd = 3.0 v 4.7 7.5 f pll = 48 mhz, f clk = 12 mhz note 2 normal operation v dd = 3.6 v 3.1 5.1 v dd = 3.0 v 3.1 5.1 f pll = 48 mhz, f clk = 6 mhz note 2 normal operation v dd = 3.6 v 2.3 3.9 v dd = 3.0 v 2.3 3.9 subsystem clock operation f sub = 32.768 khz note 4 t a = -40c normal operation square wave input 4.6 6.9 ? a resonator connection 4.7 6.9 f sub = 32.768 khz note 4 t a = +25c normal operation square wave input 4.9 7.0 resonator connection 5.0 7.2 f sub = 32.768 khz note 4 t a = +50c normal operation square wave input 5.2 7.6 resonator connection 5.2 7.7 f sub = 32.768 khz note 4 t a = +70c normal operation square wave input 5.5 9.3 resonator connection 5.6 9.4 f sub = 32.768 khz note 4 t a = +85c normal operation square wave input 6.2 13.3 resonator connection 6.2 13.4
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 32 of 149 feb 21, 2014 note 1. total current flowing into v dd , including the input leakage current flowing when the level of the input pin is fixed to v dd , or v ss . the values below the max. column include the peripher al operation current. however, not including the current flowing into the lcd controller/driver, a/d converter, d/a converter, comparator, lvd circuit, usb 2.0 function module, i/o port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. note 2. when high-speed on-chip oscillator and subsystem clock are stopped. note 3. when high-speed system clock and subsystem clock are stopped. note 4. when high-speed on-chip oscillator and high-speed system clock are stopped. when amphs1 = 1 (ultra-low power consumption oscillation). however, not including the current fl owing into the real-time clock 2, 12-bit interval timer, and watchdog timer. note 5. relationship between operation voltage width, operation frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v ? v dd ? 3.6 v@1 mhz to 24 mhz 2.4 v ? v dd ? 3.6 v@1 mhz to 16 mhz ls (low-speed main) mode: 1.8 v ? v dd ? 3.6 v@1 mhz to 8 mhz lv (low-voltage main) mode 1.6 v ? v dd ? 3.6 v@1 mhz to 4 mhz remark 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or exter nal main system clock frequency) remark 2. f hoco : high-speed on-chip oscillator clock frequency (48 mhz max.) remark 3. f ih : main system clock source frequency when the high-speed on-chip oscillator clock divided 1, 2, 4, or 8, or the pll clock divided by 2, 4, or 8 is selected (24 mhz max.) remark 4. f sub : subsystem clock frequency (xt1 clock oscillation frequency) remark 5. except subsystem clock operation, temper ature condition of the typ. value is t a = 25c
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 33 of 149 feb 21, 2014 (notes and remarks are listed on the next page.) (t a = -40 to +85 c, 1.6 v ? v dd ? 3.6 v, v ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit supply current note 1 i dd2 note 2 halt mode hs (high-speed main) mode note 7 f hoco = 48 mhz note 4 , f ih = 24 mhz note 4 v dd = 3.6 v 0.77 2.70 ma v dd = 3.0 v 0.77 2.70 f hoco = 24 mhz note 4 , f ih = 24 mhz note 4 v dd = 3.6 v 0.55 1.91 v dd = 3.0 v 0.55 1.90 f hoco = 16 mhz note 4 , f ih = 16 mhz note 4 v dd = 3.6 v 0.48 1.41 v dd = 3.0 v 0.47 1.41 ls (low-speed main) mode note 7 f hoco = 8 mhz note 4 , f ih = 8 mhz note 4 v dd = 3.0 v 300 770 ? a v dd = 2.0 v 300 770 lv (low-voltage main) mode note 7 f hoco = 4 mhz note 4 , f ih = 4 mhz note 4 v dd = 3.0 v 440 770 ? a v dd = 2.0 v 440 770 hs (high-speed main) mode note 7 f mx = 20 mhz note 3 , v dd = 3.6 v square wave input 0.35 1.63 ma resonator connection 0.51 1.68 f mx = 20 mhz note 3 , v dd = 3.0 v square wave input 0.34 1.63 resonator connection 0.51 1.68 f mx = 16 mhz note 3 , v dd = 3.6 v square wave input 0.30 1.22 resonator connection 0.45 1.39 f mx = 16 mhz note 3 , v dd = 3.0 v square wave input 0.29 1.20 resonator connection 0.45 1.38 f mx = 10 mhz note 3 , v dd = 3.6 v square wave input 0.23 0.82 resonator connection 0.30 0.90 f mx = 10 mhz note 3 , v dd = 3.0 v square wave input 0.22 0.81 resonator connection 0.30 0.89 ls (low-speed main) mode note 7 f mx = 8 mhz note 3 , v dd = 3.0 v square wave input 120 510 ? a resonator connection 170 560 f mx = 8 mhz note 3 , v dd = 2.0 v square wave input 130 520 resonator connection 170 570 hs (high-speed main) mode (pll operation) f mx = 48 mhz, f clk = 24 mhz note 3 v dd = 3.6 v 0.99 2.89 ma v dd = 3.0 v 0.99 2.88 f mx = 48 mhz, f clk = 12 mhz note 3 v dd = 3.6 v 0.89 2.48 v dd = 3.0 v 0.89 2.47 f mx = 48 mhz, f clk = 6 mhz note 3 v dd = 3.6 v 0.84 2.27 v dd = 3.0 v 0.84 2.27 subsystem clock operation f sub = 32.768 khz note 5 t a = -40c square wave input 0.32 0.61 ? a resonator connection 0.51 0.80 f sub = 32.768 khz note 5 t a = +25c square wave input 0.41 0.74 resonator connection 0.62 0.91 f sub = 32.768 khz note 5 t a = +50c square wave input 0.52 2.30 resonator connection 0.75 2.49 f sub = 32.768 khz note 5 t a = +70c square wave input 0.82 4.03 resonator connection 1.08 4.22 f sub = 32.768 khz note 5 t a = +85c square wave input 1.38 8.04 resonator connection 1.62 8.23 i dd3 note 6 stop mode note 8 t a = -40c 0.18 0.52 ? a t a = +25c 0.25 0.52 t a = +50c 0.34 2.21 t a = +70c 0.64 3.94 t a = +85c 1.18 7.95
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 34 of 149 feb 21, 2014 note 1. total current flowing into v dd , including the input leakage current flowing wh en the level of the input pin is fixed to v dd or v ss . the values below the max. column include the peripher al operation current. however, not including the current flowing into the lcd controller/driver, a/d converter, d/a converter, comparator, lvd circuit, usb 2.0 function module, i/o port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. note 2. during halt instruction ex ecution by flash memory. note 3. when high-speed on-chip oscillator and subsystem clock are stopped. note 4. when high-speed system clock and subsystem clock are stopped. note 5. when high-speed on-chip oscillator and high-speed system cl ock are stopped. when rtclpc = 1 and setting ultra-low current consumption (amphs1 = 1). the current flowing into th e real-time clock 2 is included. however, not including the current flowing into the 12-bit interval timer and watchdog timer. note 6. not including the current flowing into the real-tim e clock 2, 12-bit interval timer, and watchdog timer. note 7. relationship between operation voltage width, operation frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v ? v dd ? 3.6 v@1 mhz to 24 mhz 2.4 v ? v dd ? 3.6 v@1 mhz to 16 mhz ls (low-speed main) mode: 1.8 v ? v dd ? 3.6 v@1 mhz to 8 mhz lv (low-voltage main) mode 1.6 v ? v dd ? 3.6 v@1 mhz to 4 mhz note 8. regarding the value for current to operate the subsystem clock in stop mode, refer to that in halt mode. remark 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or exter nal main system clock frequency) remark 2. f hoco : high-speed on-chip oscillator clock frequency (48 mhz max.) remark 3. f ih : main system clock source frequency when the high-speed on-chip oscillator clock divided 1, 2, 4, or 8, or the pll clock divided by 2, 4, or 8 is selected (24 mhz max.) remark 4. f sub : subsystem clock frequency (xt1 clock oscillation frequency) remark 5. except subsystem clock operation, temper ature condition of the typ. value is t a = 25c
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 35 of 149 feb 21, 2014 (notes and remarks are listed on the next page.) (t a = -40 to +85 c, 1.6 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit low-speed on-chip oscillator operating current i fil note 1 0.20 ? a rtc2 operating current i rtc notes 1, 3 0.02 ? a 12-bit interval timer operating current i tmka notes 1, 2, 4 0.02 ? a watchdog timer operating current i wdt notes 1, 4 f il = 15 khz 0.22 ? a a/d converter operating current i adc notes 6, 7 av dd = 3.0 v, when conversion at maximum speed 422 720 ? a av ref (+) current i avref note 8 av dd = 3.0 v, adrefp1 = 0, adrefp0 = 0 note 7 14.0 25.0 ? a av refp = 3.0 v, adrefp1 = 0, adrefp0 = 1 note 10 14.0 25.0 adrefp1 = 1, adrefp0 = 0 note 1 14.0 25.0 a/d converter reference voltage current i adref notes 1, 9 v dd = 3.0 v 75.0 ? a temperature sensor operating current i tmps note 1 78 ? a d/a converter operating current i dac notes 1, 11 per d/a converter channel 0.53 1.5 ma comparator operating current i cmp notes 1, 12 v dd = 3.6 v, regulator output voltage = 2.1 v window mode 12.5 ? a comparator high-speed mode 4.5 ? a comparator low-speed mode 1.2 ? a v dd = 3.6 v, regulator output voltage = 1.8 v window mode 7.05 ? a comparator high-speed mode 2.2 ? a comparator low-speed mode 0.9 ? a lvd operating current i lvi notes 1, 13 0.06 ? a self-programming operating current i fsp notes 1, 14 2.50 12.20 ma bgo operating current i bgo notes 1, 15 1.68 12.20 ma snooze operating current i snoz note 1 adc operation the mode is performed note 16 0.34 1.10 ma the a/d conversion operations are performed, low voltage mode, av refp = v dd = 3.0 v 0.53 2.04 csi/uart operation 0.70 1.54 ma lcd operating current i lcd1 notes 17, 18 external resistance division method f lcd = f sub lcd clock = 128 hz 1/3 bias 4-time slice v dd = 3.6 v, l v4 = 3.6 v 0.14 ? a i lcd2 note 17 internal voltage boosting method f lcd = f sub lcd clock = 128 hz 1/3 bias 4-time slice v dd = 3.0 v, l v4 = 3.0 v (vlcd = 04h) 0.61 ? a i lcd3 note 17 capacitor split method f lcd = f sub lcd clock = 128 hz 1/3 bias 4-time slice v dd = 3.0 v, l v4 = 3.0 v 0.12 ? a usb current note 19 i usb note 20 operating current during usb communication 4.88 ma i usb note 21 operating current in the usb suspended state 0.04 ma
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 36 of 149 feb 21, 2014 note 1. current flowing to v dd . note 2. when high speed on-chip oscillator and high-speed system clock are stopped. note 3. current flowing only to the real-time cl ock 2 (excluding the operating current of the low-speed on-chip oscillator and the xt1 oscillator). the supply current of the rl78 microcontrollers is the sum of the values of either i dd1 or i dd2 , and i rtc , when the real-time clock 2 operates in operation mode or halt mode. when the low-speed on-chip oscillator is selected, i fil should be added. i dd2 subsystem clock operation includes the operational current of the real-time clock 2. note 4. current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and the xt1 oscillator). the supply current of the rl78 micr ocontrollers is the sum of the values of either i dd1 or i dd2 , and i tmka , when the 12-bit interval timer operates in operation m ode or halt mode. when the low-speed on-chip oscillator is selected, i fil should be added. i dd2 subsystem clock operation includes the operational current of the 12-bit interval timer. note 5. current flowing only to the watchdog time r (including the operating current of the low-speed on-chip oscillator). the current value of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i wdt when the watchdog timer operates in stop mode. note 6. current flowing only to the a/d conver ter. the supply current of the rl78 microcontrollers is the sum of i dd1 or i dd2 and i adc , i avref , i adref when the a/d converter operates in an operation mode or the halt mode. note 7. current flowing to the av dd . note 8. current flowing from the reference voltage source of a/d converter. note 9. operation current flowing to the internal reference voltage. note 10. current flowing to the av refp . note 11. current flowing only to the d/a converter. the current value of the rl78 microcontrollers is the sum of i dd1 or i dd2 and i da when the d/a converter operates in an operation mode or the halt mode. note 12. current flowing only to the comparator circuit. the curr ent value of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i cmp when the comparator circuit operates in the operating, halt or stop mode. note 13. current flowing only to the lvd circuit. the current va lue of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i lvi when the lvd circuit operates in the operating, halt or stop mode. note 14. current flowing only during self-programming. note 15. current flowing only during data flash rewrite. note 16. for shift time to the snooze mode, see 23.3.3 snooze mode in the rl78/l1c user?s manual. note 17. current flowing only to t he lcd controller/driver (v dd pin). the current value of the rl78 microcontrollers is the sum of the lcd operating current (i lcd1 , i lcd2 or i lcd3 ) to the supply current (i dd1 , or i dd2 ) when the lcd controller/driver operates in an operation mode or halt mode. not including the current that flows through the lcd panel. note 18. not including the current that flows through t he external divider resistor divider resistor. note 19. current flowing to the uv bus . note 20. including the operating current when f pll = 48 mhz. note 21. including the current supplied from the pu ll-up resistor of the udp pin to the pu ll-down resistor of the host device, in addition to the current consumed by this mcu during the suspended state. remark 1. f il : low-speed on-chip oscillator clock frequency remark 2. f sub : subsystem clock frequency (x t1 clock oscillation frequency) remark 3. f clk : cpu/peripheral hardware clock frequency remark 4. temperature condition of the typ. value is t a = 25c
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 37 of 149 feb 21, 2014 2.4 ac characteristics 2.4.1 basic operation remark f mck : timer array unit operation clock frequency (operation clock to be set by the cksmn bit of timer mode register mn (tmrmn). m: unit number (m = 0), n: channel number (n = 0 to 7)) (t a = -40 to +85 c, 1.6 v ? av dd = v dd ? 3.6 v, v ss = 0 v) (1/2) items symbol conditions min. typ. max. unit instruction cycle (minimum instruction execution time) t cy main system clock (f main ) operation hs (high-speed main) mode 2.7 v ? v dd ? 3.6 v 0.0417 1 ? s 2.4 v ? v dd < 2.7 v 0.0625 1 ? s ls (low-speed main) mode 1.8 v ? v dd ? 3.6 v 0.125 1 ? s lv (low-voltage main) mode 1.6 v ? v dd ? 3.6 v 0.25 1 ? s subsystem clock (f sub ) operation 1.8 v ? v dd ? 3.6 v 28.5 30.5 31.3 ? s in the self- programming mode hs (high-speed main) mode 2.7 v ? v dd ? 3.6 v 0.0417 1 ? s 2.4 v ? v dd < 2.7 v 0.0625 1 ? s ls (low-speed main) mode 1.8 v ? v dd ? 3.6 v 0.125 1 ? s lv (low-voltage main) mode 1.8 v ? v dd ? 3.6 v 0.25 1 ? s external main system clock frequency f ex 2.7 v ? v dd ? 3.6 v 1.0 20.0 mhz 2.4 v ? v dd < 2.7 v 1.0 16.0 mhz 1.8 v ? v dd < 2.4 v 1.0 8.0 mhz 1.6 v ? v dd < 1.8 v 1.0 4.0 mhz f ext 32 35 khz external main system clock input high-level width, low-level width t exh , t exl 2.7 v ? v dd ? 3.6 v 24 ns 2.4 v ? v dd < 2.7 v 30 ns 1.8 v ? v dd < 2.4 v 60 ns 1.6 v ? v dd < 1.8 v 120 ns t exhs , t exls 13.7 ? s ti00 to ti07 input high-level width, low-level width t tih , t til 1/f mck + 10 ns
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 38 of 149 feb 21, 2014 (t a = -40 to +85 c, 1.6 v ? av dd = v dd ? 3.6 v, v ss = 0 v) (2/2) items symbol conditions min. typ. max. unit to00 to to07, tkbo00, tkbo01, tkbo10, tkbo11, tkbo20, tkbo21 output frequency f to hs (high-speed main) mode 2.7 v ? v dd ? 3.6 v 8 mhz 2.4 v ? v dd < 2.7 v 8 mhz ls (low-speed main) mode 1.8 v ? v dd ? 3.6 v 4 mhz lv (low-voltage main) mode 1.6 v ? v dd ? 3.6 v 2 mhz pclbuz0, pclbuz1 output frequency f pcl hs (high-speed main) mode 2.7 v ? v dd ? 3.6 v 8 mhz 2.4 v ? v dd < 2.7 v 8 mhz ls (low-speed main) mode 1.8 v ? v dd ? 3.6 v 4 mhz lv (low-voltage main) mode 1.8 v ? v dd ? 3.6 v 2 mhz interrupt input high-level width, low-level width t inth , t intl intp0 to intp7 1.6 v ? v dd ? 3.6 v 1 ? s key interrupt input low-level width t kr 1.8 v ? v dd ? 3.6 v 250 ns 1.6 v ? v dd < 1.8 v 1 ? s tmkb2 forced output stop input high-level width t ihr intp0 to intp7 f clk ? 16 mhz 125 ns f clk ? 16 mhz 2 f clk reset low-level width t rsl 10 ? s
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 39 of 149 feb 21, 2014 minimum instruction execution time during main system clock operation t cy vs v dd (hs (high-speed main) mode) 1.0 0.1 0 10 1.0 2.0 3.0 4.0 3.6 2.7 0.01 2.4 0.0417 0.0625 0.05 during self programming when high-speed system clock is selected when the high-speed on-chip oscillator clock is selected cycle time t cy [s] supply voltage v dd [v]
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 40 of 149 feb 21, 2014 t cy vs v dd (ls (low-speed main) mode) t cy vs v dd (lv (low-voltage main) mode) 1.0 0.1 0 10 1.0 2.0 3.0 3.6 0.01 during self programming when high-speed system clock is selected when the high-speed on-chip oscillator clock is selected cycle time t cy [s] supply voltage v dd [v] 1.8 4.0 0.125 1.0 0.1 0 10 1.0 2.0 3.0 0.01 cycle time t cy [s] supply voltage v dd [v] 1.6 4.0 1.8 3.6 0.25 during self programming when high-speed system clock is selected when the high-speed on-chip oscillator clock is selected
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 41 of 149 feb 21, 2014 ac timing test points external system clock timing ti/to timing interrupt request input timing v ih /v oh v il /v ol v ih /v oh test points v il /v ol exclk/exclks 1/f ex 1/f exs t exl t exls t exh t exhs t til t tih 1/f to ti00 to ti07, ti10 to ti17 to00 to to07, to10 to to17, tkbo00, tkbo01, tkbo10, tkbo11, tkbo20, tkbo21 intp0 to intp7 t intl t inth
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 42 of 149 feb 21, 2014 key interrupt input timing timer kb2 input timing reset input timing t kr kr0 to kr7 intp0 to intp7 t ihr t rsl reset
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 43 of 149 feb 21, 2014 2.5 peripheral functions characteristics ac timing test points 2.5.1 serial array unit note 1. transfer rate in the snooze mode is 4800 bps only. note 2. the following conditions are required for low voltage interface. 2.4 v ? v dd < 2.7 v: max. 2.6 mbps 1.8 v ? v dd < 2.4 v: max. 1.3 mbps 1.6 v ? v dd < 1.8 v: max. 0.6 mbps note 3. the maximum operating frequencies of the cpu/peripheral hardware clock (f clk ) are: hs (high-speed main) mode: 24 mhz (2.7 v ? v dd ? 3.6 v) 16 mhz (2.4 v ? v dd ? 3.6 v) ls (low-speed main) mode: 8 mhz (1.8 v ? v dd ? 3.6 v) lv (low-voltage main) mode: 4 mhz (1.6 v ? v dd ? 3.6 v) caution select the normal input buffer for the rxdq pin and the normal output mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). (1) during communication at same potential (uart mode) (t a = -40 to +85 c, 1.6 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. transfer rate note 1 2.7 v ? v dd ? 3.6 v f mck /6 note 2 f mck /6 f mck /6 bps theoretical value of the maximum transfer rate f mck = f clk note 3 4.0 1.3 0.6 mbps 2.4 v ? v dd ? 3.6 v f mck /6 note 2 f mck /6 f mck /6 bps theoretical value of the maximum transfer rate f mck = f clk note 3 2.6 1.3 0.6 mbps 1.8 v ? v dd ? 3.6 v ? f mck /6 note 2 f mck /6 bps theoretical value of the maximum transfer rate f mck = f clk note 3 ? 1.3 0.6 mbps 1.6 v ? v dd ? 3.6 v ? ? f mck /6 bps theoretical value of the maximum transfer rate f mck = f clk note 3 ? ? 0.6 mbps v ih /v oh v il /v ol v ih /v oh test points v il /v ol
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 44 of 149 feb 21, 2014 uart mode connection diagram (during communication at same potential) uart mode bit width (durin g communication at same potential) (reference) remark 1. q: uart number (q = 0 to 3), g: pim and pom number (g = 0 to 3) remark 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13)) txdq rxdq user?s device rx tx rl78 microcontroller baud rate error tolerance txdq rxdq high-/low-bit width 1/transfer rate
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 45 of 149 feb 21, 2014 note 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 4. c is the load capacitance of the sckp and sop output lines. caution select the normal input buffer for the sip pin and the normal output mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). remark 1. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim number (g = 2) remark 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) (2) during communication at same potential (csi mo de) (master mode, sckp... internal clock output, corresponding csi00 only) (t a = -40 to +85 c, 2.7 v d v dd d 3.6 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. sckp cycle time t kcy1 t kcy1 t f clk /2 2.7 v d v dd d 3.6 v 167 250 500 ns sckp high-/ low-level width t kl1 2.7 v d v dd d 3.6 v t kcy1 /2 - 10 t kcy1 /2 - 50 t kcy1 /2 - 50 ns sip setup time (to sckp ) note 1 t sik1 2.7 v d v dd d 3.6 v 33 110 110 ns sip hold time (from sckp ) note 2 t ksi1 2.7 v d v dd d 3.6 v 10 10 10 ns delay time from sckp to sop output note 3 t kso1 c = 20 pf note 4 10 10 10 ns
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 46 of 149 feb 21, 2014 note 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 4. c is the load capacitance of the sckp and sop output lines. caution select the normal input buffer for the sip pin and the normal output mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). remark 1. p: csi number (p = 00, 10, 20, 30), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim number (g = 0 to 3) remark 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13)) (3) during communication at same potential (csi mo de) (master mode, sckp... internal clock output) (t a = -40 to +85 c, 1.6 v d v dd d 3.6 v, v ss = 0 v) parameter sym bol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. sckp cycle time t kcy1 t kcy1 t f clk /4 2.7 v d v dd d 3.6 v 167 500 1000 ns 2.4 v d v dd d 3.6 v 250 500 1000 ns 1.8 v d v dd d 3.6 v ? 500 1000 ns 1.6 v d v dd d 3.6 v ? ? 1000 ns sckp high-/ low-level width t kh1 , t kl1 2.7 v d v dd d 3.6 v t kcy1 /2 - 18 t kcy1 /2 - 50 t kcy1 /2 - 50 ns 2.4 v d v dd d 3.6 v t kcy1 /2 - 38 t kcy1 /2 - 50 t kcy1 /2 - 50 ns 1.8 v d v dd d 3.6 v ? t kcy1 /2 - 50 t kcy1 /2 - 50 ns 1.6 v d v dd d 3.6 v ? ? t kcy1 /2 - 100 ns sip setup time (to sckp ) note 1 t sik1 2.7 v d v dd d 3.6 v 44 110 110 ns 2.4 v d v dd d 3.6 v 75 110 110 ns 1.8 v d v dd d 3.6 v ? 110 110 ns 1.6 v d v dd d 3.6 v ? ? 220 ns sip hold time (from sckp ) note 2 t ksi1 2.4 v d v dd d 3.6 v 19 19 19 ns 1.8 v d v dd d 3.6 v ? 19 19 ns 1.6 v d v dd d 3.6 v ? ? 19 ns delay time from sckp to sop output note 3 t kso1 c = 30 pf note 4 2.7 v d v dd d 3.6 v 25 50 50 ns 2.4 v d v dd d 3.6 v 25 50 50 ns 1.8 v d v dd d 3.6 v ? 50 50 ns 1.6 v d v dd d 3.6 v ? ? 50 ns
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 47 of 149 feb 21, 2014 note 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 4. c is the load capacitance of the sop output lines. note 5. the maximum transfer rate when using the snooze mode is 1 mbps. caution select the normal input buffer for the sip pin and the normal output mode for the sop pin by using port input mode register g (pimg) and port output mode register g (pomg). remark 1. p: csi number (p = 00, 10, 20, 30), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim number (g = 0 to 3) remark 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13)) (4) during communication at same potential (csi mode) (slave mode, sckp... external clock input) (t a = -40 to +85 c, 1.6 v d v dd d 3.6 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. sckp cycle time note 5 t kcy2 2.7 v d v dd 3.6 v f mck ! 16 mhz 8/f mck ??n s f mck d 16 mhz 6/f mck 6/f mck 6/f mck ns 2.4 v d v dd 3.6 v 6/f mck and 500 6/f mck and 500 6/f mck and 500 ns 1.8 v d v dd 3.6 v ? 6/f mck and 750 6/f mck and 750 ns 1.6 v d v dd 3.6 v ? ? 6/f mck and 1500 ns sckp high-/ low-level width t kh2 , t kl2 2.7 v d v dd d 3.6 v t kcy2 /2 - 8 t kcy2 /2 - 8 t kcy2 /2 - 8 ns 1.8 v d v dd d 3.6 v ? t kcy2 /2 - 18 t kcy2 /2 - 18 ns 1.6 v d v dd d 3.6 v ? ? t kcy1 /2 - 66 ns sip setup time (to sckp ) note 1 t sik2 2.7 v d v dd d 3.6 v 1/f mck + 20 1/f mck + 30 1/f mck + 30 ns 2.4 v d v dd d 3.6 v 1/f mck + 30 1/f mck + 30 1/f mck + 30 ns 1.8 v d v dd 3.6 v ? 1/f mck + 30 1/f mck + 30 ns 1.6 v d v dd 3.6 v ? ? 1/f mck + 40 ns sip hold time (from sckp ) note 2 t ksi2 2.4 v d v dd 3.6 v 1/f mck + 31 1/f mck + 31 1/f mck + 31 ns 1.8 v d v dd 3.6 v ? 1/f mck + 31 1/f mck + 31 ns 1.6 v d v dd 3.6 v ? ? 1/f mck + 250 ns delay time from sckp to sop output note 3 t kso2 c = 30 pf note 4 2.7 v d v dd d 3.6 v 2/f mck + 44 2/f mck + 110 2/f mck + 110 ns 2.4 v d v dd 3.6 v 2/f mck + 75 2/f mck + 110 2/f mck + 110 ns 1.8 v d v dd 3.6 v ? 2/f mck + 110 2/f mck + 110 ns 1.6 v d v dd 3.6 v ? ? 2/f mck + 220 ns
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 48 of 149 feb 21, 2014 csi mode connection diagram (during communication at same potential) remark 1. p: csi number (p = 00, 10, 20, 30) remark 2. m: unit number, n: channel number (mn = 00 to 03, 10 to 13) sckp sop user's device sck si sip so rl78 microcontroller
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 49 of 149 feb 21, 2014 csi mode serial transfer timing (d uring communication at same potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) csi mode serial transfer timing (d uring communication at same potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) remark 1. p: csi number (p = 00, 10, 20, 30) remark 2. m: unit number, n: channel number (mn = 00 to 03, 10 to 13) sip sop t kcy1, 2 input data output data sckp t kl1, 2 t kh1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 input data output data t kcy1, 2 t kh1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 sip sop sckp t kl1, 2
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 50 of 149 feb 21, 2014 note 1. the value must also be equal to or less than f mck /4. note 2. set the f mck value to keep the hold time of sclr = ?l? and sclr = ?h?. caution select the normal input buffer and the n-ch open drain output (v dd tolerance) mode for the sdar pin and the normal output mode for the sclr pin by using port input mode register g (pimg) and port output mode register h (pomh). (5) during communication at sa me potential (simplified i 2 c mode) (t a = -40 to +85 c, 1.6 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. sclr clock frequency f scl 2.7 v ? v dd ? 3.6 v, c b = 50 pf, r b = 2.7 k ? 1000 note 1 400 note 1 400 note 1 khz 1.8 v ? v dd ? 3.6 v, c b = 100 pf, r b = 3 k ? 400 note 1 400 note 1 400 note 1 khz 1.8 v ? v dd ? 2.7 v, c b = 100 pf, r b = 5 k ? 300 note 1 300 note 1 300 note 1 khz 1.6 v ? v dd ? 1.8 v, c b = 100 pf, r b = 5 k ? ? ? 250 khz hold time when sclr = ?l? t low 2.7 v ? v dd ? 3.6 v, c b = 50 pf, r b = 2.7 k ? 475 1150 1150 ns 1.8 v ? v dd ? 3.6 v, c b = 100 pf, r b = 3 k ? 1150 1150 1150 ns 1.8 v ? v dd ? 2.7 v, c b = 100 pf, r b = 5 k ? 1550 1550 1550 ns 1.6 v ? v dd ? 1.8 v, c b = 100 pf, r b = 5 k ? ? ? 1850 ns hold time when sclr = ?h? t high 2.7 v ? v dd ? 3.6 v, c b = 50 pf, r b = 2.7 k ? 475 1150 1150 ns 1.8 v ? v dd ? 3.6 v, c b = 100 pf, r b = 3 k ? 1150 1150 1150 ns 1.8 v ? v dd ? 2.7 v, c b = 100 pf, r b = 5 k ? 1550 1550 1550 ns 1.6 v ? v dd ? 1.8 v, c b = 100 pf, r b = 5 k ? ? ? 1850 ns data setup time (reception) t su : dat 2.7 v ? v dd ? 3.6 v, c b = 50 pf, r b = 2.7 k ? 1/f mck + 85 note 2 1/f mck + 145 note 2 1/f mck + 145 note 2 ns 1.8 v ? v dd ? 3.6 v, c b = 100 pf, r b = 3 k ? 1/f mck + 145 note 2 1/f mck + 145 note 2 1/f mck + 145 note 2 ns 1.8 v ? v dd ? 2.7 v, c b = 100 pf, r b = 5 k ? 1/f mck + 230 note 2 1/f mck + 230 note 2 1/f mck + 230 note 2 ns 1.6 v ? v dd ? 1.8 v, c b = 100 pf, r b = 5 k ? ??1/f mck + 290 note 2 ns data hold time (transmission) t hd : dat 2.7 v ? v dd ? 3.6 v, c b = 50 pf, r b = 2.7 k ? 0 305 0 305 0 305 ns 1.8 v ? v dd ? 3.6 v, c b = 100 pf, r b = 3 k ? 0 355 0 355 0 355 ns 1.8 v ? v dd ? 2.7 v, c b = 100 pf, r b = 5 k ? 0 405 0 405 0 405 ns 1.6 v ? v dd ? 1.8 v, c b = 100 pf, r b = 5 k ? ? ? 0 405 ns
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 51 of 149 feb 21, 2014 simplified i 2 c mode connection diagram (during communication at same potential) simplified i 2 c mode serial transfer timing (d uring communication at same potential) remark 1. r b [ ? ]: communication line (sdar) pull-up resistance, c b [f]: communication line (sdar, sclr) load capacitance remark 2. r: iic number (r = 00, 10, 20, 30), g: pim number (g = 0 to 3), h: pom number (h = 0 to 3) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mo de register mn (smrmn). m: unit number (m = 0, 1), n: channel number (n = 0, 2), mn = 00 to 03, 10 to 13) sdar sclr user?s device sda scl v dd r b rl78 microcontroller sdar sclr 1/f scl t low t high t su: dat t hd: dat
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 52 of 149 feb 21, 2014 note 1. transfer rate in the snooze mode is 4,800 bps only. note 2. use it with v dd ? vb. note 3. the following conditions are required for low voltage interface. 2.4 v ? v dd ? 2.7 v: max. 2.6 mbps 1.8 v ? v dd ? 2.4 v: max. 1.3 mbps 1.6 v ? v dd ? 1.8 v: max. 0.6 mbps note 4. the maximum operating frequencies of the cpu/peripheral hardware clock (f clk ) are: hs (high-speed main) mode: 24 mhz (2.7 v ? v dd ? 3.6 v) 16 mhz (2.4 v ? v dd ? 3.6 v) ls (low-speed main) mode: 8 mhz (1.8 v ? v dd ? 3.6 v) lv (low-voltage main) mode: 4 mhz (1.6 v ? v dd ? 3.6 v) caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance) mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. remark 1. v b [v]: communication line voltage remark 2. q: uart number (q = 0 to 3), g: pim and pom number (g = 0 to 3) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13) (6) communication at different pote ntial (1.8 v, 2.5 v) (uart mode) (t a = -40 to +85 c, 1.8 v ? v dd ? 3.6 v, v ss = 0 v) (1/2) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. transfer rate notes 1, 2 reception 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v f mck /6 note 1 f mck /6 note 1 f mck /6 note 1 bps theoretical value of the maximum transfer rate f mck = f clk note 4 4.0 1.3 0.6 mbps 1.8 v ? v dd ? 3.3 v, 1.6 v ? v b ? 2.0 v f mck /6 notes 1, 2, 3 f mck /6 notes 1, 2, 3 f mck /6 notes 1, 2, 3 bps theoretical value of the maximum transfer rate f mck = f clk note 4 4.0 1.3 0.6 mbps
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 53 of 149 feb 21, 2014 note 1. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 2.7 v ? v dd < 3.6 v and 2.3 v ? v b ? 2.7 v note 2. this value as an example is calculated when the c onditions described in the ?conditions? column are met. refer to note 1 above to calculate the maximum tr ansfer rate under conditions of the customer. note 3. use it with v dd ? v b . note 4. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 1.8 v ? v dd < 3.3 v and 1.6 v ? v b ? 2.0 v note 5. this value as an example is calculated when the c onditions described in the ?conditions? column are met. refer to note 4 above to calculate the maximum tr ansfer rate under conditions of the customer. caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance) mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. (6) communication at different pote ntial (1.8 v, 2.5v) (uart mode) (t a = -40 to +85 c, 1.8 ? v dd ? 3.6 v, v ss = 0 v) (2/2) parameter symbo l conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. transfer rate note 2 transmission 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v note 1 note 1 note 1 bps theoretical value of the maximum transfer rate c b = 50 pf, r b = 2.7 k ? , v b = 2.3 v 1.2 note 2 1.2 note 2 1.2 note 2 mbp s 1.8 v ? v dd ? 3.3 v, 1.6 v ? v b ? 2.0 v notes 3, 4 notes 3, 4 notes 3, 4 bps theoretical value of the maximum transfer rate c b = 50 pf, r b = 5.5 k ? , v b = 1.6 v 0.43 note 5 0.43 note 5 0.43 note 5 mbp s maximum transfer rate = 1 [bps] baud rate error (theoretical value) = 1 transfer rate ? 2 - {-c b ? r b ? in (1 - )} ? 3 {-c b ? r b ? in (1 - )} ( ) ? number of transferred bits 1 transfer rate ? 100 [%] * this value is the theoretical value of the relative difference between the transmission and reception sides . 2.0 v b 2.0 v b maximum transfer rate = 1 [bps] baud rate error (theoretical value) = 1 transfer rate ? 2 - {-c b ? r b ? in (1 - )} ? 3 {-c b ? r b ? in (1 - )} ( ) ? number of transferred bits 1 transfer rate ? 100 [%] * this value is the theoretical value of the relative difference between the transmission and reception sides . 1.5 v b 1.5 v b
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 54 of 149 feb 21, 2014 uart mode connection diagram (during communication at different potential) uart mode bit width (during communicatio n at different potential) (reference) remark 1. r b [ ? ]: communication line (txdq) pull-up resistance, c b [f]: communication line (txdq) load capacitance, v b [v]: communication line voltage remark 2. q: uart number (q = 0 to 3), g: pim and pom number (g = 0 to 3) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13)) txdq rxdq user?s device rx tx v b r b rl78 microcontroller baud rate error tolerance high-/low-bit width 1/transfer rate baud rate error tolerance high-bit width low-bit width 1/transfer rate txdq rxdq
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 55 of 149 feb 21, 2014 note 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. note 2. when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance) mode for the sop pin and sckp pin by using port input mode register g (p img) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. remark 1. r b [ ]: communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sckp, sop) load capacitance, v b [v]: communication line voltage remark 2. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim and pom number (g = 2) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) (7) communication at differe nt potential (2.5 v) (csi mode) (maste r mode, sckp... internal clock output, corresponding csi00 only) (t a = -40 to +85 c, 2.7 v d v dd d 3.6 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. sckp cycle time t kcy1 t kcy1 t f clk /2 2.7v d v dd 3.6 v, 2.3 v d v b d 2.7 v, c b = 20 pf, r b = 2.7 k : 300 1150 1150 ns sckp high-level width t kh1 2.7 v d v dd 3.6 v, 2.3 v d v b d 2.7 v, c b = 20 pf, r b = 2.7 k : t kcy1 /2 - 120 t kcy1 /2 - 120 t kcy1 /2 - 120 ns sckp low-level width t kl1 2.7 v d v dd 3.6 v, 2.3 v d v b d 2.7 v, c b = 20 pf, r b = 1.4 k : t kcy1 /2 - 10 t kcy1 /2 - 50 t kcy1 /2 - 50 ns sip setup time (to sckp ) note 1 t sik1 2.7 v d v dd 3.6 v, 2.3 v d v b d 2.7 v, c b = 20 pf, r b = 2.7 k : 121 479 479 ns sip hold time (from sckp ) note 1 t ksi1 2.7 v d v dd 3.6 v, 2.3 v d v b d 2.7 v, c b = 20 pf, r b = 1.4 k : 10 10 10 ns delay time from sckp to sop output note 1 t kso1 2.7 v d v dd 3.6 v, 2.3 v d v b d 2.7 v, c b = 20 pf, r b = 1.4 k : 130 130 130 ns sip setup time (to sckp ) note 2 t sik1 2.7 v d v dd 3.6 v, 2.3 v d v b d 2.7 v, c b = 20 pf, r b = 2.7 k : 33 110 110 ns sip hold time (from sckp ) note 2 t ksi1 2.7 v d v dd 3.6 v, 2.3 v d v b d 2.7 v, c b = 20 pf, r b = 2.7 k : 10 10 10 ns delay time from sckp to sop output note 2 t kso1 2.7 v d v dd 3.6 v, 2.3 v d v b d 2.7 v, c b = 20 pf, r b = 2.7 k : 10 10 10 ns
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 56 of 149 feb 21, 2014 note use it with v dd ? v b . caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance) mode for the sop pin and sckp pin by using port input mode register g (p img) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. (remarks are listed on the page after the next page.) (8) communication at differe nt potential (1.8 v, 2.5 v) (csi mode ) (master mode, sckp... internal clock output) (t a = -40 to +85 c, 1.8 v ? v dd ? 3.6 v, v ss = 0 v) (1/2) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. sckp cycle time t kcy1 t kcy1 ? f clk /4 2.7v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 500 note 1150 1150 ns 1.8 v ? v dd ? 3.3 v, 1.6 v ? v b ? 1.8 v, c b = 30 pf, r b = 5.5 k ? 1150 note 1150 1150 ns sckp high- level width t kh1 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? t kcy1 /2 - 170 t kcy1 /2 - 170 t kcy1 /2 - 170 ns 1.8 v ? v dd ? 3.3 v, 1.6 v ? v b ? 2.0 v, c b = 30 pf, r b = 5.5 k ? t kcy1 /2 - 458 t kcy1 /2 - 458 t kcy1 /2 - 458 ns sckp low- level width t kl1 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? t kcy1 /2 - 18 t kcy1 /2 - 50 t kcy1 /2 - 50 ns 1.8 v ? v dd ? 3.3 v, 1.6 v ? v b ? 2.0 v, c b = 30 pf, r b = 5.5 k ? t kcy1 /2 - 50 t kcy1 /2 - 50 t kcy1 /2 - 50 ns
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 57 of 149 feb 21, 2014 note 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. note 2. when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 3. use it with v dd ? v b . caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance) mode for the sop pin and sckp pin by using port input mode register g (p img) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. (remarks are listed on the next page.) (8) communication at differe nt potential (1.8 v, 2.5 v) (csi mode ) (master mode, sckp... internal clock output) (t a = -40 to +85 c, 1.8 v ? v dd ? 3.6 v, v ss = 0 v) (2/2) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. sip setup time (to sckp 9) note 1 t sik1 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 177 479 479 ns 1.8 v ? v dd ? 3.3 v, 1.6 v ? v b ? 2.0 v note 3 , c b = 30 pf, r b = 5.5 k ? 479 479 479 ns sip hold time (from sckp 9) note 1 t ksi1 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 19 19 19 ns 1.8 v ? v dd ? 3.3 v, 1.6 v ? v b ? 2.0 v note 3 , c b = 30 pf, r b = 5.5 k ? 19 19 19 ns delay time from sckp ; to sop output note 1 t kso1 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 195 195 195 ns 1.8 v ? v dd ? 3.3 v, 1.6 v ? v b ? 2.0 v note 3 , c b = 30 pf, r b = 5.5 k ? 483 483 483 ns sip setup time (to sckp ;) note 2 t sik1 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 44 110 110 ns 1.8 v ? v dd ? 3.3 v, 1.6 v ? v b ? 2.0 v note 3 , c b = 30 pf, r b = 5.5 k ? 110 110 110 ns sip hold time (from sckp ;) note 2 t ksi1 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 19 19 19 ns 1.8 v ? v dd ? 3.3 v, 1.6 v ? v b ? 2.0 v note 3 , c b = 30 pf, r b = 5.5 k ? 19 19 19 ns delay time from sckp 9 to sop output note 2 t kso1 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 25 25 25 ns 1.8 v ? v dd ? 3.3 v, 1.6 v ? v b ? 2.0 v note 3 , c b = 30 pf, r b = 5.5 k ? 25 25 25 ns
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 58 of 149 feb 21, 2014 csi mode connection diagram (during communication at different potential) remark 1. r b [ ? ]: communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sckp, sop) load capacitance, v b [v]: communication line voltage remark 2. p: csi number (p = 00, 10, 20, 30), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim and pom number (g = 0 to 3) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) sckp sop user?s device sck si sip so v b r b v b r b rl78 microcontroller
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 59 of 149 feb 21, 2014 csi mode serial transfer timing (master mode ) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) csi mode serial transfer timing (master mode ) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) remark p: csi number (p = 00, 10, 20, 30), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim and pom number (g = 0 to 3) input data sip sop t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 output data sckp input data output data sip sop sckp t kcy1 t kh1 t kl1 t sik1 t ksi1 t kso1
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 60 of 149 feb 21, 2014 (notes and caution are listed on the next page. re marks are listed on the page after the next page.) (9) communication at different potential (1.8 v, 2.5 v) (csi mode) (slave mode, sckp... external clock input) (t a = -40 to +85 c, 1.8 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. sckp cycle time note 1 t kcy2 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v 20 mhz < f mck ? 24 mhz 16/f mck ??n s 16 mhz < f mck ? 20 mhz 14/f mck ??n s 8 mhz < f mck ? 16 mhz 12/f mck ??n s 4 mhz < f mck ? 8 mhz 8/f mck 16/f mck ?n s f mck ? 4 mhz 6/f mck 10/f mck 10/f mck ns 1.8 v ? v dd < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 20 mhz < f mck ? 24 mhz 36/f mck ??n s 16 mhz < f mck ? 20 mhz 32/f mck ??n s 8 mhz < f mck ? 16 mhz 26/f mck ??n s 4 mhz < f mck ? 8 mhz 16/f mck 16/f mck ?n s f mck ? 4 mhz 10/f mck 10/f mck 10/f mck ns sckp high-/ low-level width t kh2 , t kl2 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v t kcy2 /2 - 18 t kcy2 /2 - 50 t kcy2 /2 - 50 ns 1.8 v ? v dd < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 t kcy2 /2 - 50 t kcy2 /2 - 50 t kcy2 /2 - 50 ns sip setup time (to sckp 9) note 3 t sik2 2.7 v ? v dd ? 3.6 v 1/f mck + 20 1/f mck + 30 1/f mck + 30 ns 1.8 v ? v dd < 3.3 v 1/f mck + 30 1/f mck + 30 1/f mck + 30 ns sip hold time (from sckp 9) note 4 t ksi2 1/f mck + 31 1/f mck + 31 1/f mck + 31 ns delay time from sckp ; to sop output note 5 t kso2 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v c b = 30 pf, r b = 2.7 k ? 2/f mck + 214 2/f mck + 573 2/f mck + 573 ns 1.8 v ? v dd < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 c b = 30 pf, r b = 5.5 k ? 2/f mck + 573 2/f mck + 573 2/f mck + 573 ns
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 61 of 149 feb 21, 2014 note 1. transfer rate in the snooze mode: max. 1 mbps note 2. use it with v dd ? v b . note 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ; ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 4. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ; ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 5. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp 9 ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. caution select the ttl input buffer for the sip pin and sckp pin and the n-ch open drain output (v dd tolerance) mode for the sop pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. (remarks are listed on the next page.)
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 62 of 149 feb 21, 2014 csi mode connection diagram (during communication at different potential) remark 1. r b [ ? ]: communication line (sop) pull-up resistance, c b [f]: communication line (sop) load capacitance, v b [v]: communication line voltage remark 2. p: csi number (p = 00, 10, 20, 30), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim and pom number (g = 0 to 3) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00, 02, 10, 12)) sckp sop user?s device sck si sip so v b r b rl78 microcontroller
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 63 of 149 feb 21, 2014 csi mode serial transfer timing (slave mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) csi mode serial transfer timing (slave mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) remark p: csi number (p = 00, 10, 20, 30), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim and pom number (g = 0 to 3) sip sop sckp input data output data t kcy2 t kh2 t kl2 t sik2 t ksi2 t kso2 input data output data sip sop sckp t kcy2 t kl2 t kh2 t sik2 t ksi2 t kso2
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 64 of 149 feb 21, 2014 note 1. the value must also be equal to or less than f mck /4. note 2. use it with v dd ? v b . note 3. set the f mck value to keep the hold time of sclr = ?l? and sclr = ?h?. caution select the ttl input buffer and the n-ch open drain output (v dd tolerance) mode for the sdar pin and the n-ch open drain output (v dd tolerance) mode for the sclr pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. (remarks are listed on the next page.) (10) communication at different potential (1.8 v, 2.5 v) (simplified i 2 c mode) (t a = -40 to +85 c, 1.8 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. sclr clock frequency f scl 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b < 2.7 v, c b = 50 pf, r b = 2.7 k ? 1000 note 1 300 note 1 300 note 1 khz 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b <2.7 v, c b = 100 pf, r b = 2.7 k ? 400 note 1 300 note 1 300 note 1 khz 1.8 v ? v dd < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 , c b = 100 pf, r b = 5.5 k ? 400 note 1 300 note 1 300 note 1 khz hold time when sclr = ?l? t low 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b < 2.7 v, c b = 50 pf, r b = 2.7 k ? 475 1550 1550 ns 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b <2.7 v, c b = 100 pf, r b = 2.7 k ? 1150 1550 1550 ns 1.8 v ? v dd < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 , c b = 100 pf, r b = 5.5 k ? 1550 1550 1550 ns hold time when sclr = ?h? t high 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b < 2.7 v, c b = 50 pf, r b = 2.7 k ? 200 610 610 ns 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b < 2.7 v, c b = 100 pf, r b = 2.7 k ? 600 610 610 ns 1.8 v ? v dd < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 , c b = 100 pf, r b = 5.5 k ? 610 610 610 ns data setup time (reception) t su:dat 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b < 2.7 v, c b = 50 pf, r b = 2.7 k ? 1/f mck + 135 note 3 1/f mck + 190 note 3 1/f mck + 190 note 3 ns 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b < 2.7 v, c b = 100 pf, r b = 2.7 k ? 1/f mck + 190 note 3 1/f mck + 190 note 3 1/f mck + 190 note 3 ns 1.8 v ? v dd < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 , c b = 100 pf, r b = 5.5 k ? 1/f mck + 190 note 3 1/f mck + 190 note 3 1/f mck + 190 note 3 ns data hold time (transmission) t hd:dat 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b < 2.7 v, c b = 50 pf, r b = 2.7 k ? 0 305 0 305 0 305 ns 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b < 2.7 v, c b = 100 pf, r b = 2.7 k ? 0 355 0 355 0 355 ns 1.8 v ? v dd < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 , c b = 100 pf, r b = 5.5 k ? 0 405 0 405 0 405 ns
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 65 of 149 feb 21, 2014 simplified i 2 c mode connection diagram (during communication at different potential) simplified i 2 c mode serial transfer timing (durin g communication at different potential) remark 1. r b [ ? ]: communication line (sdar, sclr) pull-up resistance, c b [f]: communication line (sdar, sclr) load capacitance, v b [v]: communication line voltage remark 2. r: iic number (r = 00, 10, 20, 30), g: pim, pom number (g = 0 to 3) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number (m = 0, 1), n: channel number (n = 0, 2), mn = 00, 02, 10, 12) sdar sclr user?s device sda scl v b r b v b r b rl78 microcontroller sdar sclr 1/f scl t low t high t su: dat t hd: dat
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 66 of 149 feb 21, 2014 2.5.2 serial interface iica note 1. the first clock pulse is generated after this period when the start/restart condition is detected. note 2. the maximum value (max.) of t hd:dat is during normal transfer and a wait state is inserted in the ack (acknowledge) timing. remark the maximum value of c b (communication line capacitance) and the value of r b (communication line pull-up resistor) at that time in each mode are as follows. standard mode: c b = 400 pf, r b = 2.7 k ? (1) i 2 c standard mode (t a = -40 to +85 c, 1.6 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. scla0 clock frequency f scl standard mode: f clk ? 1 mhz 2.7 v ? v dd ? 3.6 v 0 100 0 100 0 100 khz 1.8 v ? v dd ? 3.6 v ? ? 0 100 0 100 khz 1.6 v ? v dd ? 3.6 v ? ? ? ? 0 100 khz setup time of restart condition t su: sta 2.7 v ? v dd ? 3.6 v 4.7 4.7 4.7 ? s 1.8 v ? v dd ? 3.6 v ? 4.7 4.7 ? s 1.6 v ? v dd ? 3.6 v ? ? 4.7 ? s hold time note 1 t hd: sta 2.7 v ? v dd ? 3.6 v 4.0 4.0 4.0 ? s 1.8 v ? v dd ? 3.6 v ? 4.0 4.0 ? s 1.6 v ? v dd ? 3.6 v ? ? 4.0 ? s hold time when scla0 = ?l? t low 2.7 v ? v dd ? 3.6 v 4.7 4.7 4.7 ? s 1.8 v ? v dd ? 3.6 v ? 4.7 4.7 ? s 1.6 v ? v dd ? 3.6 v ? ? 4.7 ? s hold time when scla0 = ?h? t high 2.7 v ? v dd ? 3.6 v 4.0 4.0 4.0 ? s 1.8 v ? v dd ? 3.6 v ? 4.0 4.0 ? s 1.6 v ? v dd ? 3.6 v ? ? 4.0 ? s data setup time (reception) t su: dat 2.7 v ? v dd ? 3.6 v 250 250 250 ns 1.8 v ? v dd ? 3.6 v ? 250 250 ns 1.6 v ? v dd ? 3.6 v ? ? 250 ns data hold time (transmission) note 2 t hd: dat 2.7 v ? v dd ? 3.6 v 0 3.45 0 3.45 0 3.45 ? s 1.8 v ? v dd ? 3.6 v ? ? 0 3.45 0 3.45 ? s 1.6 v ? v dd ? 3.6 v ? ? ? ? 0 3.45 ? s setup time of stop condition t su: sto 2.7 v ? v dd ? 3.6 v 4.0 4.0 4.0 ? s 1.8 v ? v dd ? 3.6 v ? 4.0 4.0 ? s 1.6 v ? v dd ? 3.6 v ? ? 4.0 ? s bus-free time t buf 2.7 v ? v dd ? 3.6 v 4.7 4.7 4.7 ? s 1.8 v ? v dd ? 3.6 v ? 4.7 4.7 ? s 1.6 v ? v dd ? 3.6 v ? ? 4.7 ? s
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 67 of 149 feb 21, 2014 note 1. the first clock pulse is generated after this period when the start/restart condition is detected. note 2. the maximum value (max.) of t hd: dat is during normal transfer and a wait st ate is inserted in the ack (acknowledge) timing. remark the maximum value of c b (communication line capacitance) and the value of r b (communication line pull-up resistor) at that time in each mode are as follows. fast mode: c b = 320 pf, r b = 1.1 k ? (2) i 2 c fast mode (t a = -40 to +85 c, 1.8 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. scla0 clock frequency f scl fast mode: f clk ? 3.5 mhz 2.7 v ? v dd ? 3.6 v 0 400 0 400 0 400 khz 1.8 v ? v dd ? 3.6 v 0 400 0 400 0 400 khz setup time of restart condition t su: sta 2.7 v ? v dd ? 3.6 v 0.6 0.6 0.6 ? s 1.8 v ? v dd ? 3.6 v 0.6 0.6 0.6 ? s hold time note 1 t hd: sta 2.7 v ? v dd ? 3.6 v 0.6 0.6 0.6 ? s 1.8 v ? v dd ? 3.6 v 0.6 0.6 0.6 ? s hold time when scla0 = ?l? t low 2.7 v ? v dd ? 3.6 v 1.3 1.3 1.3 ? s 1.8 v ? v dd ? 3.6 v 1.3 1.3 1.3 ? s hold time when scla0 = ?h? t high 2.7 v ? v dd ? 3.6 v 0.6 0.6 0.6 ? s 1.8 v ? v dd ? 3.6 v 0.6 0.6 0.6 ? s data setup time (reception) t su: dat 2.7 v ? v dd ? 3.6 v 100 100 100 ns 1.8 v ? v dd ? 3.6 v 100 100 100 ns data hold time (transmission) note 2 t hd: dat 2.7 v ? v dd ? 3.6 v 0 0.9 0 0.9 0 0.9 ? s 1.8 v ? v dd ? 3.6 v 0 0.9 0 0.9 0 0.9 ? s setup time of stop condition t su: sto 2.7 v ? v dd ? 3.6 v 0.6 0.6 0.6 ? s 1.8 v ? v dd ? 3.6 v 0.6 0.6 0.6 ? s bus-free time t buf 2.7 v ? v dd ? 3.6 v 1.3 1.3 1.3 ? s 1.8 v ? v dd ? 3.6 v 1.3 1.3 1.3 ? s
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 68 of 149 feb 21, 2014 note 1. the first clock pulse is generated after this period when the start/restart condition is detected. note 2. the maximum value (max.) of t hd: dat is during normal transfer and a wait st ate is inserted in the ack (acknowledge) timing. remark the maximum value of c b (communication line capacitance) and the value of r b (communication line pull-up resistor) at that time in each mode are as follows. fast mode plus: c b = 120 pf, r b = 1.1 k ? iica serial transfer timing (3) i 2 c fast mode plus (t a = -40 to +85 c, 2.7 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode ls (low-speed main) mode lv (low-voltage main) mode unit min. max. min. max. min. max. scla0 clock frequency f scl fast mode plus: f clk ? 10 mhz 2.7 v ? v dd ? 3.6 v 0 1000 ? ? khz setup time of restart condition t su: sta 2.7 v ? v dd ? 3.6 v 0.26 ? ? ? s hold time note 1 t hd: sta 2.7 v ? v dd ? 3.6 v 0.26 ? ? ? s hold time when scla0 = ?l? t low 2.7 v ? v dd ? 3.6 v 0.5 ? ? ? s hold time when scla0 = ?h? t high 2.7 v ? v dd ? 3.6 v 0.26 ? ? ? s data setup time (reception) t su: dat 2.7 v ? v dd ? 3.6 v 50 ? ? ns data hold time (transmission) note 2 t hd: dat 2.7 v ? v dd ? 3.6 v 0 0.45 ? ? ? s setup time of stop condition t su: sto 2.7 v ? v dd ? 3.6 v 0.26 ? ? ? s bus-free time t buf 2.7 v ? v dd ? 3.6 v 0.5 ? ? ? s t su: dat t hd: sta restart condition scln sdan t low t high t su: sta t hd: sta t su: sto stop condition stop condition start condition t hd: dat t buf
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 69 of 149 feb 21, 2014 2.5.3 usb note value of instantaneous voltage note excludes the first signal transition from the idle state. (1) electrical specifications (t a = -40 to +85 c, 2.4 v ? v dd ? 3.6 v, v ss = 0 v, hs (high-speed main) mode only) parameter symbol conditions min. typ. max. unit u regc u regc output voltage characteristic u regc uv bus = 4.0 to 5.5 v, pxxcon = vddusbe = 1 3.0 3.3 3.6 v uv bus uv bus input voltage characteristic uv bus function 4.35 (4.02 note ) 5.00 5.25 v (t a = -40 to +85 c, 4.35 v ? uv bus ? 5.25 v, 2.4 v ? v dd ? 3.6 v, v ss = 0 v, hs (high-speed main) mode only) parameter symbol conditions min. typ. max. unit input characteristic (fs/ls receiver) input voltage v ih 2.0 v v il 0.8 v difference input sensitivity v di | udp voltage - udm voltage | 0.2 v difference common mode range v cm 0.8 2.5 v output characteristic (fs driver) output voltage v oh i oh = -200 ? a2 . 8 3 . 6 v v ol i ol = 2 ma 0 0.3 v transition time rising t fr rising: from 10% to 90% of amplitude, falling: from 90% to 10% of amplitude, cl = 50 pf 420ns falling t ff 42 0n s matching (tfr/tff) v frfm 90 111.1 % crossover voltage v fcrs 1.3 2.0 v output impedance z drv 28 44 ? output characteristic (ls driver) output voltage v oh 2.8 3.6 v v ol 00 . 3v transition time rising t lr rising: from 10% to 90% of amplitude, falling: from 90% to 10% of amplitude, cl = 250 pf to 750 pf the udp and udm pins ar e individually pulled down via 15 k ? 75 300 ns falling t lf 75 300 ns matching (tfr/tff) note v ltfm 80 125 % crossover voltage note v lcrs 1.3 2.0 v pull-up, pull-down pull-down resistor r pd 14.25 24.80 k ? pull-up resistor idle r pui 0.9 1.575 k ? reception r pua 1.425 3.09 k ? uv bus uv bus pull-down resistor r vbus uv bus voltage = 5.5 v 1000 k ? uv bus input voltage v ih 3.20 v v il 0.8 v
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 70 of 149 feb 21, 2014 timing of udp and udm (2) bc standard (t a = -40 to +85 c, 4.35 v ? uv bus ? 5.25 v, 2.4 v ? v dd ? 3.6 v, v ss = 0 v, hs (high-speed main) mode only) parameter symbol conditions min. typ. max. unit usb standard bc1.2 udp sink current i dp_sink 25 100 175 ? a udm sink current i dm_sink 25 100 175 ? a dcd source current i dp_src 71013 ? a data detection voltage v dat_ref 0.25 0.325 0.4 v udp source voltage v dp_src output current 250 ? a 0.5 0.6 0.7 v udm source voltage v dm_src output current 250 ? a 0.5 0.6 0.7 v udp udm 10% v crs (crossover voltage) 90% 90% 10% t r t f
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 71 of 149 feb 21, 2014 (3) bc option standard (t a = -40 to +85 c, 4.35 v ? uv bus ? 5.25 v, 2.4 v ? v dd ? 3.6 v, v ss = 0 v, hs (high-speed main) mode only) parameter symbol conditions min. typ. max. unit udp/udm input reference voltage (uv bus divider ratio) (function) vdseli [3: 0] (i = 0, 1) 0000 v ddet0 27 32 37 %uvbus 0001 v ddet1 29 34 39 %uvbus 0010 v ddet2 32 37 42 %uvbus 0011 v ddet3 35 40 45 %uvbus 0100 v ddet4 38 43 48 %uvbus 0101 v ddet5 41 46 51 %uvbus 0110 v ddet6 44 49 54 %uvbus 0111 v ddet7 47 52 57 %uvbus 1000 v ddet8 51 56 61 %uvbus 1001 v ddet9 55 60 65 %uvbus 1010 v ddet10 59 64 69 %uvbus 1011 v ddet11 63 68 73 %uvbus 1100 v ddet12 67 72 73 %uvbus 1101 v ddet13 71 76 81 %uvbus 1110 v ddet14 75 80 85 %uvbus 1111 vd det15 79 84 89 %uvbus
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 72 of 149 feb 21, 2014 2.6 analog characteristics 2.6.1 a/d converte r characteristics note 1. typ. value is the average value at av dd = av refp = 3 v and t a = 25 ? c. max. value is the average value 3 1 at normalized distribution. note 2. these values are the results of characterist ic evaluation and are not checked for shipment. note 3. excludes quantization error (1/2 lsb). caution 1. route the wiring so that noise will not be supe rimposed on each power line and ground line, and insert a capacitor to suppress noise. in addition, separate the reference voltage line of av refp from the other power lines to keep it free from the influences of noise. caution 2. during a/d conversion, keep a pulse, such as a digital signal, that abruptly changes its level from being input to or output from the pins adjacent to the converter pins and p150 to p156. classification of a/d converter characteristics reference voltage input channel reference voltage (+) = av refp reference voltage (-) = av refm reference voltage (+) = av dd reference voltage (-) = av ss reference voltage (+) = internal reference voltage reference voltage (-) = av ss high-accuracy channel; ani0 to ani6 (input buffer power supply: av dd ) refer to 2.6.1 (1) . refer to 2.6.1 (2) . refer to 2.6.1 (3) . refer to 2.6.1 (6) . standard channel; ani16 to ani21 (input buffer power supply: v dd ) refer to 2.6.1 (4) . refer to 2.6.1 (5) . internal reference voltage, temperature sensor output voltage refer to 2.6.1 (4) . refer to 2.6.1 (5) .? (1) when reference voltage (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage (-) = av refm /ani1 (adrefm = 1), target fo r conversion: ani2 to ani6 (t a = -40 to +85 c, 2.7 v ? av refp ? av dd = v dd ? 3.6 v, v ss = 0 v, av ss = 0 v, reference voltage (+) = av refp , reference voltage (-) = av refm = 0 v, halt mode) parameter symbol conditions min. typ. max. unit resolution r es 12 bit overall error notes 1, 2, 3 ainl 12-bit resolution ? 1.7 ? 3.3 lsb conversion time t conv adtyp = 0, 12-bit resolution 3.375 ? s zero-scale error notes 1, 2, 3 e zs 12-bit resolution ? 1.3 ? 3.2 lsb full-scale error notes 1, 2, 3 e fs 12-bit resolution ? 0.7 ? 2.9 lsb integral linearity error notes 1, 2, 3 ile 12-bit resolution ? 1.0 ? 1.4 lsb differential linearity error notes 1, 2, 3 dle 12-bit resolution ? 0.9 ? 1.2 lsb analog input voltage v ain 0a v refp v
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 73 of 149 feb 21, 2014 note 1. cannot be used for lower 2 bit of adcr register note 2. cannot be used for lower 4 bit of adcr register note 3. excludes quantization error ( ? 1/2 lsb). caution always use av dd pin with the same potential as the v dd pin. (2) when reference voltage (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage (-) = av refm /ani1 (adrefm = 1), conver sion target: ani2 to ani6 (t a = -40 to +85 c, 1.6 v ? av refp ? av dd = v dd ? 3.6 v, v ss = 0 v, av ss = 0 v, reference voltage (+) = av refp , reference voltage (-) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 2.4 v ? av refp ? av dd ? 3.6 v 8 12 bit 1.8 v ? av refp ? av dd ? 3.6 v 8 10 note 1 1.6 v ? av refp ? av dd ? 3.6 v 8 note 2 overall error note 3 ainl 12-bit resolution 2.4 v ? av refp ? av dd ? 3.6 v ? 6.0 lsb 10-bit resolution 1.8 v ? av refp ? av dd ? 3.6 v ? 5.0 8-bit resolution 1.6 v ? av refp ? av dd ? 3.6 v ? 2.5 conversion time t conv adtyp = 0, 12-bit resolution 2.4 v ? av refp ? av dd ? 3.6 v 3.375 ? s adtyp = 0, 10-bit resolution note 1 1.8 v ? av refp ? av dd ? 3.6 v 6.75 adtyp = 0, 8-bit resolution note 2 1.6 v ? av refp ? av dd ? 3.6 v 13.5 adtyp = 1, 8-bit resolution 2.4 v ? av refp ? av dd ? 3.6 v 2.5625 1.8 v ? av refp ? av dd ? 3.6 v 5.125 1.6 v ? av refp ? av dd ? 3.6 v 10.25 zero-scale error note 3 e zs 12-bit resolution 2.4 v ? av refp ? av dd ? 3.6 v ? 4.5 lsb 10-bit resolution 1.8 v ? av refp ? av dd ? 3.6 v ? 4.5 8-bit resolution 1.6 v ? av refp ? av dd ? 3.6 v ? 2.0 full-scale error note 3 e fs 12-bit resolution 2.4 v ? av refp ? av dd ? 3.6 v ? 4.5 lsb 10-bit resolution 1.8 v ? av refp ? av dd ? 3.6 v ? 4.5 8-bit resolution 1.6 v ? av refp ? av dd ? 3.6 v ? 2.0 integral linearity error note 3 ile 12-bit resolution 2.4 v ? av refp ? av dd ? 3.6 v ? 2.0 lsb 10-bit resolution 1.8 v ? av refp ? av dd ? 3.6 v ? 1.5 8-bit resolution 1.6 v ? av refp ? av dd ? 3.6 v ? 1.0 differential linearity error note 3 dle 12-bit resolution 2.4 v ? av refp ? av dd ? 3.6 v ? 1.5 lsb 10-bit resolution 1.8 v ? av refp ? av dd ? 3.6 v ? 1.5 8-bit resolution 1.6 v ? av refp ? av dd ? 3.6 v ? 1.0 analog input voltage v ain 0a v refp v
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 74 of 149 feb 21, 2014 note 1. cannot be used for lower 2 bit of adcr register note 2. cannot be used for lower 4 bit of adcr register note 3. excludes quantization error ( ? 1/2 lsb). caution always use av dd pin with the same potential as the v dd pin. (3) when reference voltage (+) = av dd (adrefp1 = 0, adrefp0 = 0), reference voltage (-) = av ss (adrefm = 0), conversion target: ani0 to ani6 (t a = -40 to +85 c, 1.6 v ? av dd = v dd ? 3.6 v, v ss = 0 v, av ss = 0 v, reference voltage (+) = av dd , reference voltage (-) = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 2.4 v ? av dd ? 3.6 v 8 12 bit 1.8 v ? av dd ? 3.6 v 8 10 note 1 1.6 v ? av dd ? 3.6 v 8 note 2 overall error note 3 ainl 12-bit resolution 2.4 v ? av dd ? 3.6 v ? 7.5 lsb 10-bit resolution 1.8 v ? av dd ? 3.6 v ? 5.5 8-bit resolution 1.6 v ? av dd ? 3.6 v ? 3.0 conversion time t conv adtyp = 0, 12-bit resolution 2.4 v ? av dd ? 3.6 v 3.375 ? s adtyp = 0, 10-bit resolution note 1 1.8 v ? av dd ? 3.6 v 6.75 adtyp = 0, 8-bit resolution note 2 1.6 v ? av dd ? 3.6 v 13.5 adtyp = 1, 8-bit resolution 2.4 v ? av dd ? 3.6 v 2.5625 1.8 v ? av dd ? 3.6 v 5.125 1.6 v ? av dd ? 3.6 v 10.25 zero-scale error note 3 e zs 12-bit resolution 2.4 v ? av dd ? 3.6 v ? 6.0 lsb 10-bit resolution 1.8 v ? av dd ? 3.6 v ? 5.0 8-bit resolution 1.6 v ? av dd ? 3.6 v ? 2.5 full-scale error note 3 e fs 12-bit resolution 2.4 v ? av dd ? 3.6 v ? 6.0 lsb 10-bit resolution 1.8 v ? av dd ? 3.6 v ? 5.0 8-bit resolution 1.6 v ? av dd ? 3.6 v ? 2.5 integral linearity error note 3 ile 12-bit resolution 2.4 v ? av dd ? 3.6 v ? 3.0 lsb 10-bit resolution 1.8 v ? av dd ? 3.6 v ? 2.0 8-bit resolution 1.6 v ? av dd ? 3.6 v ? 1.5 differential linearity error note 3 dle 12-bit resolution 2.4 v ? av dd ? 3.6 v ? 2.0 lsb 10-bit resolution 1.8 v ? av dd ? 3.6 v ? 2.0 8-bit resolution 1.6 v ? av dd ? 3.6 v ? 1.5 analog input voltage v ain ani0 to ani6 0 av dd v
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 75 of 149 feb 21, 2014 note 1. cannot be used for lower 2 bits of adcr register note 2. cannot be used for lower 4 bits of adcr register note 3. excludes quantization error ( ? 1/2 lsb). note 4. refer to 2.6.2 temperature sensor, internal reference voltage output characteristics . caution always use av dd pin with the same potential as the v dd pin. (4) when reference voltage (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage (-) = av refm /ani1 (adrefm = 1), conversion target: ani16 to an i21, internal reference voltage, temperature sensor output voltage (t a = -40 to +85 c, 1.6 v ? v dd ? 3.6 v, 1.6 v ? av refp ? av dd = v dd ? 3.6 v, v ss = 0 v, av ss = 0 v, reference voltage (+) = av refp , reference voltage (-) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 2.4 v ? av refp ? av dd ? 3.6 v 8 12 bit 1.8 v ? av refp ? av dd ? 3.6 v 8 10 note 1 1.6 v ? av refp ? av dd ? 3.6 v 8 note 2 overall error note 3 ainl 12-bit resolution 2.4 v ? av refp ? av dd ? 3.6 v ? 7.0 lsb 10-bit resolution 1.8 v ? av refp ? av dd ? 3.6 v ? 5.5 8-bit resolution 1.6 v ? av refp ? av dd ? 3.6 v ? 3.0 conversion time t conv adtyp = 0, 12-bit resolution 2.4 v ? av refp ? av dd ? 3.6 v 4.125 ? s adtyp = 0, 10-bit resolution note 1 1.8 v ? av refp ? av dd ? 3.6 v 9.5 adtyp = 0, 8-bit resolution note 2 1.6 v ? av refp ? av dd ? 3.6 v 57.5 adtyp = 1, 8-bit resolution 2.4 v ? av refp ? av dd ? 3.6 v 3.3125 1.8 v ? av refp ? av dd ? 3.6 v 7.875 1.6 v ? av refp ? av dd ? 3.6 v 54.25 zero-scale error note 3 e zs 12-bit resolution 2.4 v ? av refp ? av dd ? 3.6 v ? 5.0 lsb 10-bit resolution 1.8 v ? av refp ? av dd ? 3.6 v ? 5.0 8-bit resolution 1.6 v ? av refp ? av dd ? 3.6 v ? 2.5 full-scale error note 3 e fs 12-bit resolution 2.4 v ? av refp ? av dd ? 3.6 v ? 5.0 lsb 10-bit resolution 1.8 v ? av refp ? av dd ? 3.6 v ? 5.0 8-bit resolution 1.6 v ? av refp ? av dd ? 3.6 v ? 2.5 integral linearity error note 3 ile 12-bit resolution 2.4 v ? av refp ? av dd ? 3.6 v ? 3.0 lsb 10-bit resolution 1.8 v ? av refp ? av dd ? 3.6 v ? 2.0 8-bit resolution 1.6 v ? av refp ? av dd ? 3.6 v ? 1.5 differential linearity error note 3 dle 12-bit resolution 2.4 v ? av refp ? av dd ? 3.6 v ? 2.0 lsb 10-bit resolution 1.8 v ? av refp ? av dd ? 3.6 v ? 2.0 8-bit resolution 1.6 v ? av refp ? av dd ? 3.6 v ? 1.5 analog input voltage v ain 0a v refp v internal reference voltage (2.4 v ? v dd ? 3.6 v, hs (high-speed main) mode) v bgr note 4 temperature sensor output voltage (2.4 v ? v dd ? 3.6 v, hs (high-speed main) mode) v tmp25 note 4
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 76 of 149 feb 21, 2014 note 1. cannot be used for lower 2 bits of adcr register note 2. cannot be used for lower 4 bits of adcr register note 3. excludes quantization error ( ? 1/2 lsb). note 4. refer to 2.6.2 temperature sensor, internal reference voltage output characteristics . caution always use av dd pin with the same potential as the v dd pin. (5) when reference voltage (+) = av dd (adrefp1 = 0, adrefp0 = 0), reference voltage (-) = av ss (adrefm = 0), conversion target: ani16 to ani21, internal reference voltage, temperature sensor output voltage (t a = -40 to +85 c, 1.6 v ? v dd ? 3.6 v, 1.6 v ? av dd = v dd ? 3.6 v, v ss = 0 v, av ss = 0 v, reference voltage (+) = av dd , reference voltage (-) = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 2.4 v ? av dd ? 3.6 v 8 12 bit 1.8 v ? av dd ? 3.6 v 8 10 note 1 1.6 v ? av dd ? 3.6 v 8 note 2 overall error note 3 ainl 12-bit resolution 2.4 v ? av dd ? 3.6 v ? 8.5 lsb 10-bit resolution 1.8 v ? av dd ? 3.6 v ? 6.0 8-bit resolution 1.6 v ? av dd ? 3.6 v ? 3.5 conversion time t conv adtyp = 0, 12-bit resolution 2.4 v ? av dd ? 3.6 v 4.125 ? s adtyp = 0, 10-bit resolution note 1 1.8 v ? av dd ? 3.6 v 9.5 adtyp = 0, 8-bit resolution note 2 1.6 v ? av dd ? 3.6 v 57.5 adtyp = 1, 8-bit resolution 2.4 v ? av dd ? 3.6 v 3.3125 1.8 v ? av dd ? 3.6 v 7.875 1.6 v ? av dd ? 3.6 v 54.25 zero-scale error note 3 e zs 12-bit resolution 2.4 v ? av dd ? 3.6 v ? 8.0 lsb 10-bit resolution 1.8 v ? av dd ? 3.6 v ? 5.5 8-bit resolution 1.6 v ? av dd ? 3.6 v ? 3.0 full-scale error note 3 e fs 12-bit resolution 2.4 v ? av dd ? 3.6 v ? 8.0 lsb 10-bit resolution 1.8 v ? av dd ? 3.6 v ? 5.5 8-bit resolution 1.6 v ? av dd ? 3.6 v ? 3.0 integral linearity error note 3 ile 12-bit resolution 2.4 v ? av dd ? 3.6 v ? 3.5 lsb 10-bit resolution 1.8 v ? av dd ? 3.6 v ? 2.5 8-bit resolution 1.6 v ? av dd ? 3.6 v ? 1.5 differential linearity error note 3 dle 12-bit resolution 2.4 v ? av dd ? 3.6 v ? 2.5 lsb 10-bit resolution 1.8 v ? av dd ? 3.6 v ? 2.5 8-bit resolution 1.6 v ? av dd ? 3.6 v ? 2.0 analog input voltage v ain 0a v dd v internal reference voltage (2.4 v ? v dd ? 3.6 v, hs (high-speed main) mode) v bgr note 4 temperature sensor output voltage (2.4 v ? v dd ? 3.6 v, hs (high-speed main) mode) v tmp25 note 4
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 77 of 149 feb 21, 2014 note excludes quantization error (1/2 lsb). caution always use av dd pin with the same potential as the v dd pin. 2.6.2 temperature sensor, internal re ference voltage output characteristics 2.6.3 d/a converter characteristics (6) when reference voltage (+) = internal reference vo ltage (1.45 v) (adrefp1 = 1, adrefp0 = 0), reference voltage (-) = av ss (adrefm = 0), conversion targe t: ani0 to ani6, ani16 to ani21 (t a = -40 to +85 c, 2.4 v ? v dd ? 3.6 v, 1.6 v ? v dd , 1.6 v ? av dd = v dd , v ss = 0 v, av ss = 0 v, reference voltage (+) = internal reference voltage, reference voltage (-) = av ss = 0 v, hs (high-speed main) mode) parameter symbol conditions min. typ. max. unit resolution r es 8b i t conversion time t conv 8-bit resolution 16 ? s zero-scale error note e zs 8-bit resolution ? 4.0 lsb integral linearity error note ile 8-bit resolution ? 2.0 lsb differential linearity error note dle 8-bit resolution ? 2.5 lsb reference voltage (+) av ref(+) = internal reference voltage (v bgr ) 1.38 1.45 1.5 v analog input voltage v ain 0v bgr v (t a = -40 to +85 c, 2.4 v ? v dd ? 3.6 v, v ss = 0 v (hs (high-speed main) mode)) parameter symbol conditions min. typ. max. unit temperature sensor output voltage v tmps25 setting ads register = 80h, t a = +25 ? c1 . 0 5 v internal reference voltage v bgr setting ads register = 81h 1.38 1.45 1.5 v temperature coefficient f vtmps temperature sensor output voltage that depends on the temperature -3.6 mv/c operation stabilization wait time t amp 10 ? s (t a = -40 to +85 c, 1.6 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 8bit overall error ainl rload = 4 m ? 1.8 v ? v dd ? 3.6 v ? 2.5 lsb rload = 8 m ? 1.8 v ? v dd ? 3.6 v ? 2.5 lsb settling time t set cload = 20 pf 2.7 v ? v dd ? 3.6 v 3 ? s 1.6 v ? v dd < 2.7 v 6 ? s
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 78 of 149 feb 21, 2014 2.6.4 comparator note not usable in ls (low-speed main) mode, lv (low-voltage main) mode, sub-clock operation, or stop mode. 2.6.5 por circuit characteristics note minimum time required for a por reset when v dd exceeds below v pdr . this is also the minimum time required for a por reset from when v dd exceeds below 0.7 v to when v dd exceeds v por while stop mode is entered or the main system clock is stopped through setting bit 0 (hiostop) and bit 7 (mstop) in the clock operation status control register (csc). (t a = -40 to +85 c, 1.6 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit input voltage range ivref 0 v dd - 1.4 v ivcmp -0.3 v dd + 0.3 v output delay td v dd = 3.0 v input slew rate > 50 mv/ ? s high-speed comparator mode, standard mode 1.2 ? s high-speed comparator mode, window mode 2.0 ? s low-speed comparator mode, standard mode 35.0 ? s high-electric-potential judgment voltage vtw+ high-speed comparator mode, window mode 0.76 v dd v low-electric-potential judgment voltage vtw- high-speed comparator mode, window mode 0.24 v dd v operation stabilization wait time t cmp 100 ? s internal reference voltage note v bgr 1.38 1.45 1.50 v (t a = -40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage v por power supply rise time 1.47 1.51 1.55 v v pdr power supply fall time note 1.46 1.50 1.54 v minimum pulse width t pw 300 ? s t pw v por v pdr or 0.7 v supply voltage (v dd )
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 79 of 149 feb 21, 2014 2.6.6 lvd circuit characteristics caution set the detection voltage (v lvd ) to be within the operating voltage range. the operating voltage range depends on the setting of the user option byte (000c2h/010c2h). the following shows the operating voltage range. hs (high-speed main) mode: v dd = 2.7 to 3.6 v at 1 mhz to 24 mhz v dd = 2.4 to 3.6 v at 1 mhz to 16 mhz ls (low-speed main) mode: v dd = 1.8 to 3.6 v at 1 mhz to 8 mhz lv (low-voltage main) mode: v dd = 1.6 to 3.6 v at 1 mhz to 4 mhz (t a = -40 to +85 c, v pdr ? v dd ? 3.6 v ? v ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage supply voltage level v lvd2 power supply rise time 3.07 3.13 3.19 v power supply fall time 3.00 3.06 3.12 v v lvd3 power supply rise time 2.96 3.02 3.08 v power supply fall time 2.90 2.96 3.02 v v lvd4 power supply rise time 2.86 2.92 2.97 v power supply fall time 2.80 2.86 2.91 v v lvd5 power supply rise time 2.76 2.81 2.87 v power supply fall time 2.70 2.75 2.81 v v lvd6 power supply rise time 2.66 2.71 2.76 v power supply fall time 2.60 2.65 2.70 v v lvd7 power supply rise time 2.56 2.61 2.66 v power supply fall time 2.50 2.55 2.60 v v lvd8 power supply rise time 2.45 2.50 2.55 v power supply fall time 2.40 2.45 2.50 v v lvd9 power supply rise time 2.05 2.09 2.13 v power supply fall time 2.00 2.04 2.08 v v lvd10 power supply rise time 1.94 1.98 2.02 v power supply fall time 1.90 1.94 1.98 v v lvd11 power supply rise time 1.84 1.88 1.91 v power supply fall time 1.80 1.84 1.87 v v lvd12 power supply rise time 1.74 1.77 1.81 v power supply fall time 1.70 1.73 1.77 v v lvd13 power supply rise time 1.64 1.67 1.70 v power supply fall time 1.60 1.63 1.66 v minimum pulse width t lw 300 ? s detection delay time 300 ? s
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 80 of 149 feb 21, 2014 2.7 power supply voltage ri sing slope ch aracteristics caution make sure to keep the internal reset state by the lvd circuit or an external reset until v dd reaches the operating voltage range shown in 2.4 ac characteristics. lvd detection voltage of interrupt & reset mode (t a = -40 to +85 c, v pdr ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit interrupt and reset mode v lvda0 v poc0 , v poc1 , v poc2 = 0, 0, 0, falling reset voltage: 1.6 v 1.60 1.63 1.66 v v lvda1 lvis0, lvis1 = 1, 0 rising release reset voltage 1.74 1.77 1.81 v falling interrupt voltage 1.70 1.73 1.77 v v lvda2 lvis0, lvis1 = 0, 1 rising release reset voltage 1.84 1.88 1.91 v falling interrupt voltage 1.80 1.84 1.87 v v lvda3 lvis0, lvis1 = 0, 0 rising release reset voltage 2.86 2.92 2.97 v falling interrupt voltage 2.80 2.86 2.91 v v lvdb0 v poc0 , v poc1 , v poc2 = 0, 0, 1, falling reset voltage: 1.8 v 1.80 1.84 1.87 v v lvdb1 lvis0, lvis1 = 1, 0 rising release reset voltage 1.94 1.98 2.02 v falling interrupt voltage 1.90 1.94 1.98 v v lvdb2 lvis0, lvis1 = 0, 1 rising release reset voltage 2.05 2.09 2.13 v falling interrupt voltage 2.00 2.04 2.08 v v lvdb3 lvis0, lvis1 = 0, 0 rising release reset voltage 3.07 3.13 3.19 v falling interrupt voltage 3.00 3.06 3.12 v v lvdc0 v poc0 , v poc1 , v poc2 = 0, 1, 0, falling reset voltage: 2.4 v 2.40 2.45 2.50 v v lvdc1 lvis0, lvis1 = 1, 0 rising release reset voltage 2.56 2.61 2.66 v falling interrupt voltage 2.50 2.55 2.60 v v lvdc2 lvis0, lvis1 = 0, 1 rising release reset voltage 2.66 2.71 2.76 v falling interrupt voltage 2.60 2.65 2.70 v v lvdd0 v poc0 , v poc1 , v poc2 = 0, 1, 1, falling reset voltage: 2.7 v 2.70 2.75 2.81 v v lvdd1 lvis0, lvis1 = 1, 0 rising release reset voltage 2.86 2.92 2.97 v falling interrupt voltage 2.80 2.86 2.91 v v lvdd2 lvis0, lvis1 = 0, 1 rising release reset voltage 2.96 3.02 3.08 v falling interrupt voltage 2.90 2.96 3.02 v (t a = -40 to +85 c, v ss = 0 v) parameter conditions min. typ. max. unit power supply voltage rising slope sv dd 54 v/ms
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 81 of 149 feb 21, 2014 2.8 lcd characteristics 2.8.1 resistance division method (1) static display mode (t a = -40 to +85 c, v l4 (min.) ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit lcd drive voltage v l4 2.0 v dd v (2) 1/2 bias method, 1/4 bias method (t a = -40 to +85 c, v l4 (min.) ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit lcd drive voltage v l4 2.7 v dd v (3) 1/3 bias method (t a = -40 to +85 c, v l4 (min.) ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit lcd drive voltage v l4 2.5 v dd v
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 82 of 149 feb 21, 2014 2.8.2 internal voltage boosting method note 1. this is a capacitor that is connected between voltage pins used to drive the lcd. c1: a capacitor connected between caph and capl c2: a capacitor connected between v l1 and gnd c3: a capacitor connected between v l2 and gnd c4: a capacitor connected between v l4 and gnd c1 = c2 = c3 = c4 = 0.47 ? f ? 30% note 2. this is the time required to wait from when the reference voltage is specified by using the vlcd register (or when the internal voltage boosting method is selected (by setting the mdset1 and mdset0 bits of the lcdm0 register to 01b) if the default value reference voltage is used) until voltage boosting starts (vlcon = 1). note 3. this is the wait time from when voltage boosting is star ted (vlcon = 1) until display is enabled (lcdon = 1). (1) 1/3 bias method (t a = -40 to +85 c, 1.8 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit lcd output voltage variation range v l1 c1 to c4 note 1 = 0.47 ? f note 2 vlcd = 04h 0.90 1 .00 1.08 v vlcd = 05h 0.95 1.05 1.13 v vlcd = 06h 1.00 1.1 0 1.18 v vlcd = 07h 1.05 1.15 1.23 v vlcd = 08h 1.10 1.2 0 1.28 v vlcd = 09h 1.15 1.25 1.33 v vlcd = 0ah 1.20 1.3 0 1.38 v vlcd = 0bh 1.25 1.35 1.43 v vlcd = 0ch 1.30 1.40 1.48 v vlcd = 0dh 1.35 1.45 1.53 v vlcd = 0eh 1.40 1.5 0 1.58 v vlcd = 0fh 1.45 1.55 1.63 v vlcd = 10h 1.50 1.6 0 1.68 v vlcd = 11h 1.55 1.65 1.73 v vlcd = 12h 1.60 1.7 0 1.78 v vlcd = 13h 1.65 1.75 1.83 v doubler output voltage v l2 c1 to c4 note 1 = 0.47 ? f 2 v l1 - 0.1 2 v l1 2 v l1 v tripler output voltage v l3 c1 to c4 note 1 = 0.47 ? f 3 v l1 - 0.15 3 v l1 3 v l1 v reference voltage setup time note 2 t vwait1 5m s voltage boost wait time note 3 t vwait2 c1 to c4 note 1 = 0.47 ? f 500 ms
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 83 of 149 feb 21, 2014 note 1. this is a capacitor that is connected between voltage pins used to drive the lcd. c1: a capacitor connected between caph and capl c2: a capacitor connected between v l1 and gnd c3: a capacitor connected between v l2 and gnd c4: a capacitor connected between v l3 and gnd c5: a capacitor connected between v l4 and gnd c1 = c2 = c3 = c4 = 0.47 ? f ? 30% note 2. this is the time required to wait from when the reference voltage is specified by using the vlcd register (or when the internal voltage boosting method is selected (by setting the mdset1 and mdset0 bits of the lcdm0 register to 01b) if the default value reference voltage is used) until voltage boosting starts (vlcon = 1). note 3. this is the wait time from when voltage boosting is star ted (vlcon = 1) until display is enabled (lcdon = 1). (2) 1/4 bias method (t a = -40 to +85 c, 1.8 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit lcd output voltage variation range v l1 c1 to c4 note 1 = 0.47 ? f note 2 vlcd = 04h 0.90 1 .00 1.08 v vlcd = 05h 0.95 1.05 1.13 v vlcd = 06h 1.00 1.1 0 1.18 v vlcd = 07h 1.05 1.15 1.23 v vlcd = 08h 1.10 1.2 0 1.28 v vlcd = 09h 1.15 1.25 1.33 v vlcd = 0ah 1.20 1.3 0 1.38 v doubler output voltage v l2 c1 to c4 note 1 = 0.47 ? f 2 v l1 - 0.08 2 v l1 2 v l1 v tripler output voltage v l3 c1 to c4 note 1 = 0.47 ? f 3 v l1 - 0.12 3 v l1 3 v l1 v quadruply output voltage v l4 c1 to c5 note 1 = 0.47 ? f 4 v l1 - 0.16 4 v l1 4 v l1 v reference voltage setup time note 2 t vwait1 5m s voltage boost wait time note 3 t vwait2 c1 to c5 note 1 = 0.47 ? f 500 ms
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 84 of 149 feb 21, 2014 2.8.3 capacitor split method note 1. this is the wait time from when voltage bucking is started (vlcon = 1) until display is enabled (lcdon = 1). note 2. this is a capacitor that is connected between voltage pins used to drive the lcd. c1: a capacitor connected between caph and capl c2: a capacitor connected between v l1 and gnd c3: a capacitor connected between v l2 and gnd c4: a capacitor connected between v l4 and gnd c1 = c2 = c3 = c4 = 0.47 ? f ? 30% (1) 1/3 bias method (t a = -40 to +85 c, 2.2 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit v l4 voltage v l4 c1 to c4 = 0.47 ? f note 2 v dd v v l2 voltage v l2 c1 to c4 = 0.47 ? f note 2 2/3 v l4 - 0.1 2/3 v l4 2/3 v l4 + 0.1 v v l1 voltage v l1 c1 to c4 = 0.47 ? f note 2 1/3 v l4 - 0.1 1/3 v l4 1/3 v l4 + 0.1 v capacitor split wait time note 1 t vwait 100 ms
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 85 of 149 feb 21, 2014 2.9 data memory stop mode low supply voltage data retention characteristics note the value depends on the por detection voltage. when the vo ltage drops, the data is retained before a por reset is effected, but data is not retained when a por reset is effected. 2.10 flash memory programming characteristics note 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. the retaining years are until next rewrite after the rewrite. note 2. when using flash memory programmer and renes as electronics self programming library note 3. these are the characteristics of the fl ash memory and the results obtained from reliability testing by renesas electronics corporation. 2.11 dedicated flash memory programmer communication (uart) (t a = -40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.46 note 3.6 v (t a = -40 to +85 c, 1.8 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit cpu/peripheral hardware clock frequency f clk 2.4 v ? v dd ? 3.6 v 124mhz number of code flash rewrites notes 1, 2, 3 c erwr retained for 20 years t a = 85 ? c 1,000 times number of data flash rewrites notes 1, 2, 3 retained for 1 year t a = 25 ? c 1,000,000 retained for 5 years t a = 85 ? c 100,000 retained for 20 years t a = 85 ? c 10,000 (t a = -40 to +85 c, 1.8 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit transfer rate during serial programming 115,200 1,000,000 bps v dd stop instruction execution standby release signal (interrupt request) stop mode data retention mode operation mode v dddr
rl78/l1c 2. electrical specifications (a: t a = -40 to +85 c) r01ds0192ej0200 rev. 2.00 page 86 of 149 feb 21, 2014 2.12 timing specs for switching modes <1> the low level is input to the tool0 pin. <2> the external reset ends (por and lvd reset must end before the external reset ends.). <3> the tool0 pin is set to the high level. <4> setting of the flash memory programming mode by uart reception and complete the baud rate setting. remark t suinit : the segment shows that it is necessary to finish spec ifying the initial communication settings within 100 ms from when the resets end. t su : how long from when the tool0 pin is placed at the low level until a external reset ends t hd: how long to keep the tool0 pin at the low level from when the external and internal resets end (except soft processing time) (t a = -40 to +85 c, 1.8 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit how long from when an external reset ends until the initial communication se ttings are specified t suinit por and lvd reset must end before the external reset ends. 100 ms how long from when the tool0 pin is placed at the low level until an external reset ends t su por and lvd reset must end before the external reset ends. 10 ? s time to hold the tool0 pin at the low level after an external reset is releas ed (excluding the processing time of the firmware to control the flash memory) t hd por and lvd reset must end before the external reset ends. 1ms reset tool0 <1> <2> <3> t su <4> t suinit 723 s + t hd processing time 00h reception (toolrxd, tooltxd mode)
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 87 of 149 feb 21, 2014 3. electrical spec ifications (g: t a = -40 to +105 c) this chapter describes the electrical specifications for the products ?g: industrial applications (t a = -40 to +105 ?c)?. caution 1. the rl78 microcontroller has an on-chip debug function, which is provided for development and evaluation. do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. caution 2. the pins mounted depend on the product. refer to 1.3.1 80-pin products (with usb) to 1.3.6 100-pin products (without usb). caution 3. please contact renesas electronics sal es office for derating of operation under t a = +85 ? c to +105 ? c. derating is the systematic reduction of load for the sake of improved reliability. remark when the rl78 microcontroller is used in the range of t a = -40 to +85 ?c, see 2. electrical specifications (a: t a = -40 to +85 c) . the following functions differ between the products ?g: industrial applications (t a = -40 to +105 ? c)? and the products ?a: consumer applications and g: industrial applications (when used in the range of t a = -40 to +85 ? c)?. remark the electrical characteristics of t he products g: industr ial applications (t a = -40 to +105 c) are different from those of the products ?a: consumer applications?. for details, refer to 3.1 to 3.12 . parameter a: consumer applicat ions g: industrial applications operating ambient temperature t a = -40 to +85 c t a = -40 to +105 c operating mode operating voltage range hs (high-speed main) mode: 2.7 v ? v dd ? 3.6 v@1 mhz to 24 mhz 2.4 v ? v dd ? 3.6 v@1 mhz to 16 mhz ls (low-speed main) mode: 1.8 v ? v dd ? 3.6 v@1 mhz to 8 mhz lv (low-voltage main) mode: 1.6 v ? v dd ? 3.6 v@1 mhz to 4 mhz hs (high-speed main) mode only: 2.7 v ? v dd ? 3.6 v@1 mhz to 24 mhz 2.4 v ? v dd ? 3.6 v@1 mhz to 16 mhz high-speed on-chip oscillator clock accuracy 1.8 v ? v dd ? 3.6 v: 1.0% @ t a = -20 to +85 c 1.5% @ t a = -40 to -20 c 1.6 v ? v dd ? 1.8 v: 5.0% @ t a = -20 to +85 c 5.5% @ t a = -40 to -20 c 2.4 v ? v dd ? 3.6 v: 2.0% @ t a = +85 to +105 c 1.0% @ t a = -20 to +85 c 1.5% @ t a = -40 to -20 c serial array unit uart csi: f clk /4 simplified i 2 c communication uart csi: f clk /4 simplified i 2 c communication iica normal mode fast mode fast mode plus normal mode fast mode voltage detector ? rise detection voltage: 1.67 v to 3.13 v (12 levels) ? fall detection voltage: 1.63 v to 3.06 v (12 levels) ? rise detection voltage: 2.61 v to 3.13 v (6 levels) ? fall detection voltage: 2.55 v to 3.06 v (6 levels)
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 88 of 149 feb 21, 2014 3.1 absolute maximum ratings note 1. connect the regc pin to v ss via a capacitor (0.47 to 1 ? f). this value regulates the absolute maximum rating of the regc pin. do not use this pin with voltage applied to it. note 2. connect the u regc pin to vss via a capacitor (0.33 ? f). this value regulates the absolute maximum rating of the u regc pin. do not use this pin with voltage applied to it. note 3. must be 6.5 v or lower. note 4. must be 4.6 v or lower. note 5. do not exceed av ref(+) + 0.3 v in case of a/d conversion target pin. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark 1. unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. remark 2. av ref (+) : + side reference voltage of the a/d converter. remark 3. v ss : reference voltage absolute maximum ratings (t a = 25 ?c) (1/3) parameter symbols conditions ratings unit supply voltage v dd -0.5 to + 6.5 v uv bus -0.5 to + 6.5 v av dd av dd ? ? v dd -0.5 to + 4.6 v regc pin input voltage v iregc regc -0.3 to + 2.8 and -0.3 to v dd + 0.3 note 1 v u regc pin input voltage v iuregc u regc -0.3 to uv bus + 0.3 note 2 v input voltage v i1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p46, p50 to p57, p70 to p77, p80 to p83, p125 to p127, p137, p140 to p143, exclk, exclks, reset -0.3 to v dd + 0.3 note 3 v v i2 p60, p61 (n-ch open-drain) -0.3 to + 6.5 v v i3 udp, udm -0.3 to + 6.5 v v i4 p150 to p156 -0.3 to av dd + 0.3 note 4 v output voltage v o1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p46, p50 to p57, p60, p61, p70 to p77, p80 to p83, p125 to p127, p140 to p143 -0.3 to v dd + 0.3 note 3 v v o2 p130, p150 to p156 -0.3 to av dd + 0.3 note 3 v v o3 udp, udm -0.3 to + 3.8 v analog input voltage v ai1 ani16 to ani21 -0.3 to v dd + 0.3 and av ref(+) + 0.3 notes 3, 5 v v ai2 ani0 to ani6 -0.3 to av dd + 0.3 and av ref(+) + 0.3 notes 3, 5 v
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 89 of 149 feb 21, 2014 note 1. this value only indicates the absolute maxi mum ratings when applying voltage to the v l1 , v l2 , v l3 , and v l4 pins; it does not mean that applying voltage to these pins is recommen ded. when using the internal voltage boosting method or capacitance split method, connect these pins to v ss via a capacitor (0.47 ? 30%) and connect a capacitor (0.47 ? 30%) between the capl and caph pins. note 2. must be 6.5 v or lower. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. absolute maximum ratings (t a = 25 ?c) (2/3) parameter symbols conditions ratings unit lcd voltage v li1 v l1 input voltage note 1 -0.3 to +2.8 v v li2 v l2 input voltage note 1 -0.3 to +6.5 v v li3 v l3 input voltage note 1 -0.3 to +6.5 v v li4 v l4 input voltage note 1 -0.3 to +6.5 v v li5 capl, caph input voltage note 1 -0.3 to +6.5 v v lo1 v l1 output voltage -0.3 to +2.8 v v lo2 v l2 output voltage -0.3 to +6.5 v v lo3 v l3 output voltage -0.3 to +6.5 v v lo4 v l4 output voltage -0.3 to +6.5 v v lo5 capl, caph output voltage -0.3 to +6.5 v v lo6 com0 to com7 seg0 to seg55 output voltage external resistance division method -0.3 to v dd + 0.3 note 2 v capacitor split method -0.3 to v dd + 0.3 note 2 v internal voltage boosting method -0.3 to v li4 + 0.3 note 2 v
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 90 of 149 feb 21, 2014 caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. absolute maximum ratings (t a = 25 ?c) (3/3) parameter symbols conditions ratings unit output current, high i oh1 per pin p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p46, p50 to p57, p70 to p77, p80 to p83, p125 to p127, p140 to p143 -40 ma total of all pins -170 ma p40 to p46 -70 ma p00 to p07, p10 to p17, p20 to p27, p30 to p37, p50 to p57, p70 to p77, p80 to p83, p125 to p127, p140 to p143 -100 ma i oh2 per pin p130, p150 to p156 -0.1 ma total of all pins -0.8 ma i oh3 per pin udp, udm -3 ma output current, low i ol1 per pin p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p46, p50 to p57, p60, p61, p70 to p77, p80 to p83, p125 to p127, p140 to p143 40 ma total of all pins 170 ma p40 to p46 70 ma p00 to p07, p10 to p17, p20 to p27, p30 to p37, p50 to p57, p70 to p77, p80 to p83, p125 to p127, p140 to p143 100 ma i ol2 per pin p130, p150 to p156 0.4 ma total of all pins 3.2 ma i ol3 per pin udp, udm 3 ma operating ambient temperature t a in normal operation mode -40 to +105 ? c in flash memory programming mode -40 to +85 storage temperature t stg -65 to +150 ? c
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 91 of 149 feb 21, 2014 3.2 oscillator characteristics 3.2.1 x1 and xt1 oscill ator characteristics note indicates only permissible oscillat or frequency ranges. refer to ac characteristics for instruction execution time. request evaluation by the manufacturer of the oscilla tor circuit mounted on a boa rd to check the oscillator characteristics. caution since the cpu is started by the high-speed on-chip oscillator clock after a reset release, check the x1 clock oscillation stabilization time using the oscillation stabilization time counter status register (ostc) by the user. determine the oscillation stabilization time of the ostc register and the oscillation stabilization time select register (osts) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. remark when using the x1 and xt1 oscillator, refer to 5.4 system clock oscillator in the rl78/l1c user?s manual. (t a = -40 to +105 c, 2.4 v ? v dd ? 3.6 v, v ss = 0 v) parameter resonator conditions min. typ. max. unit x1 clock oscillation frequency (f x ) note ceramic resonator/crystal resonator 2.7 v ? ? v dd ? ? 3.6 v 1.0 20.0 mhz 2.4 v ? ? v dd < 2.7 v 1.0 16.0 xt1 clock oscillation frequency (f xt ) note crystal resonator 32 32.768 35 khz
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 92 of 149 feb 21, 2014 3.2.2 on-chip oscillator characteristics note 1. high-speed on-chip oscillator fr equency is selected with bits 0 to 4 of the opt ion byte (000c2h) and bits 0 to 2 of the hocodiv register. note 2. this only indicates t he oscillator characte ristics. refer to ac characteristics for instruction execution time. 3.2.3 pll oscillator characteristics note indicates only oscillator c haracteristics. refer to ac characteristics for instruction execution time. (t a = -40 to +105 c, 2.4 v ? v dd ? 3.6 v, v ss = 0 v) oscillators parameters conditions min. typ. max. unit high-speed on-chip oscillator clock frequency notes 1, 2 f hoco 12 4m h z high-speed on-chip oscillator clock frequency accuracy -20 to +85 ? c -1.0 +1.0 % -40 to -20 ? c -1.5 +1.5 % +85 to +105 ? c -2.0 +2.0 % low-speed on-chip oscillator clock frequency f il 15 khz low-speed on-chip oscillator clock frequency accuracy -15 +15 % (t a = -40 to +105 c, 2.4 v ? v dd ? 3.6 v, v ss = 0 v) oscillators parameters conditions min. typ. max. unit pll input frequency note f pllin high-speed system clock 6.00 16.00 mhz pll output frequency note f pll 48.00 mhz
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 93 of 149 feb 21, 2014 3.3 dc characteristics 3.3.1 pin characteristics note 1. value of current at which the device operation is guaranteed even if the current flows from the v dd pin to an output pin. note 2. however, do not exceed the total current value. note 3. specification under conditions where the duty factor is 70%. the output current value that has changed the duty ratio c an be calculated with the following expression (when changing the duty factor from 70% to n%). ? total output current of pins = (i oh ? 0.7)/(n ? 0.01) where n = 50% and i oh = -10.0 ma total output current of pins = (-10.0 ? 0.7)/(50 ? 0.01) = -14.0 ma however, the current that is allowed to flow into one pin does not vary depending on the duty factor. a current higher than the absolute maximum rating must not flow into one pin. caution p00 to p02, p10 to p12, p24 to p26, p33 to p35, and p42 to p44 do not output high level in n-ch open-drain mode. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (t a = -40 to +105 c, 2.4 v ? av dd = v dd ? 3.6 v, v ss = 0 v) items symbol conditions min. typ. max. unit output current, high note 1 i oh1 per pin for p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p46, p50 to p57, p70 to p77, p80 to p83, p125 to p127, p140 to p143 -10.0 note 2 ma total of p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p46, p50 to p57, p70 to p77, p80 to p83, p125 to p127, p140 to p143 (when duty = 70% note 3 ) 2.7 v ? v dd ? 3.6 v -15.0 ma 2.4 v ? v dd < 2.7 v -7.0 ma i oh2 per pin for p130, p150 to p156 -0.1 note 2 ma total of all pins 2.4 v ? v dd ? 3.6 v -0.8 ma
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 94 of 149 feb 21, 2014 note 1. value of current at which the device operation is guaranteed even if the current flows from an output pin to the v ss pin. note 2. however, do not exceed the total current value. note 3. specification under conditions where the duty factor is 70%. the output current value that has changed the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). ? total output current of pins = (i ol ? 0.7)/(n ? 0.01) where n = 50% and i ol = 10.0 ma total output current of pins = (10.0 ? 0.7)/(50 ? 0.01) = 14.0 ma however, the current that is allowed to flow in to one pin does not vary depending on the duty factor. a current higher than the absolute maximum rating must not flow into one pin. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (t a = -40 to +105 c, 2.4 v ? av dd = v dd ? 3.6 v, v ss = 0 v) items symbol conditions min. typ. max. unit output current, low note 1 i ol1 per pin for p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p46, p50 to p57, p60, p61, p70 to p77, p80 to p83, p125 to p127, p140 to p143 20.0 note 2 ma per pin for p60 and p61 15.0 note 2 ma total of p40 to p46 (when duty = 70% note 3 ) 2.7 v ? v dd ? 3.6 v 15.0 ma 2.4 v ? v dd < 2.7 v 9.0 ma total of p00 to p07, p10 to p17, p20 to p27, p30 to p37, p50 to p57, p60, p61, p70 to p77, p80 to p83, p125 to p127, p140 to p143 (when duty = 70% note 3 ) 2.7 v ? v dd ? 3.6 v 35.0 ma 2.4 v ? v dd < 2.7 v 20.0 ma total of all pins (when duty = 70% note 3 ) 50.0 ma i ol2 per pin for p130, p150 to p156 0.4 note 2 ma total of all pins 2.4 v ? v dd ? 3.6 v 3.2 ma
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 95 of 149 feb 21, 2014 caution the maximum value of v ih of pins p00 to p02, p10 to p12, p24 to p26, p33 to p35, and p42 to p44 is v dd , even in the n-ch open-drain mode. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (t a = -40 to +105 c, 2.4 v ? av dd = v dd ? 3.6 v, v ss = 0 v) items symbol conditions min. typ. max. unit input voltage, high v ih1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p46, p50 to p57, p70 to p77, p80 to p83, p125 to p127, p140 to p143 normal input buffer 0.8 v dd v dd v v ih2 p00, p01, p10, p11, p24, p25, p33, p34, p43, p44 ttl input buffer 3.3 v ? v dd ? 3.6 v 2.0 v dd v ttl input buffer 2.4 v ? v dd < 3.3 v 1.50 v dd v v ih3 p150 to p156 0.7 av dd av dd v v ih4 p60, p61 0.7 v dd 6.0 v v ih5 p121 to p124, p137, exclk, exclks, reset 0.8 v dd v dd v input voltage, low v il1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p46, p50 to p57, p70 to p77, p80 to p83, p125 to p127, p140 to p143 normal input buffer 0 0.2 v dd v v il2 p00, p01, p10, p11, p24, p25, p33, p34, p43, p44 ttl input buffer 3.3 v ? v dd ? 3.6 v 00.5v ttl input buffer 2.4 v ? v dd < 3.3 v 00.32v v il3 p150 to p156 0 0.3 av dd v v il4 p60, p61 0 0.3 v dd v v il5 p121 to p124, p137, exclk, exclks, reset 0 0.2 v dd v
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 96 of 149 feb 21, 2014 caution p00 to p02, p10 to p12, p24 to p26, p33 to p35, and p42 to p44 do not output high level in n-ch open-drain mode. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (t a = -40 to +105 c, 2.4 v ? av dd = v dd ? 3.6 v, v ss = 0 v) items symbol conditions min. typ. max. unit output voltage, high v oh1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p46, p50 to p57, p70 to p77, p80 to p83, p125 to p127, p140 to p143 2.7 v ? v dd ? 3.6 v, i oh1 = -2.0 ma v dd - 0.6 v 2.4 v ? v dd ? 3.6 v, i oh1 = -1.5 ma v dd - 0.5 v v oh2 p130, p150 to p156 2.4 v ? v dd ? 3.6 v, i oh2 = -100 ? a av dd - 0.5 v output voltage, low v ol1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p46, p50 to p57, p70 to p77, p80 to p83, p125 to p127, p140 to p143 2.7 v ? v dd ? 3.6 v, i ol1 = 3.0 ma 0.6 v 2.4 v ? v dd ? 3.6 v, i ol1 = 1.5 ma 0.4 v 2.4 v ? v dd ? 3.6 v, i ol1 = 0.6 ma 0.4 v v ol2 p130, p150 to p156 2.4 v ? v dd ? 3.6 v, i ol2 = 400 ? a 0.4 v v ol3 p60, p61 2.7 v ? v dd ? 3.6 v, i ol3 = 3.0 ma 0.4 v 2.4 v ? v dd ? 3.6 v, i ol3 = 2.0 ma 0.4 v
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 97 of 149 feb 21, 2014 remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (t a = -40 to +105 c, 2.4 v ? av dd = v dd ? 3.6 v, v ss = 0 v) items symbol conditions min. typ. max. unit input leakage current, high i lih1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p46, p50 to p57, p60, p61, p70 to p77, p80 to p83, p125 to p127, p137, p140 to p143, reset v i = v dd 1 ? a i lih2 p20, p21, p140 to p143 v i = v dd 1 ? a i lih3 p121 to p124 (x1, x2, exclk, xt1, xt2, exclks) v i = v dd in input port or external clock input 1 ? a in resonator connection 10 ? a i lih4 p150 to p156 v i = av dd 1 ? a input leakage current, low i lil1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p46, p50 to p57, p60, p61, p70 to p77, p80 to p83, p125 to p127, p137, p140 to p143, reset v i = v ss -1 ? a i lil2 p20, p21, p140 to p143 v i = v ss -1 ? a i lil3 p121 to p124 (x1, x2, exclk, xt1, xt2, exclks) v i = v ss in input port or external clock input -1 ? a in resonator connection -10 ? a i lil4 p150 to p156 v i = av ss -1 ? a on-chip pull-up resistance r u1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p50 to p57, p70 to p77, p140 to p143, p125 to p127 v i = v ss 2.4 v ? v dd ? 3.6 v 10 20 100 k ? r u2 p40 to p46, p80 to p83 v i = v ss 10 20 100 k ?
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 98 of 149 feb 21, 2014 3.3.2 supply current characteristics (notes and remarks are listed on the next page.) (t a = -40 to +105 c, 2.4 v ? v dd ? 3.6 v, v ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit supply current note 1 i dd1 operating mode hs (high-speed main) mode note 5 f hoco = 48 mhz note 3 , f ih = 24 mhz note 3 basic operation v dd = 3.6 v 2.2 2.9 ma v dd = 3.0 v 2.2 2.9 normal operation v dd = 3.6 v 4.4 9.2 v dd = 3.0 v 4.4 9.2 f hoco = 24 mhz note 3 , f ih = 24 mhz note 3 basic operation v dd = 3.6 v 2.0 2.6 v dd = 3.0 v 2.0 2.6 normal operation v dd = 3.6 v 4.2 7.0 v dd = 3.0 v 4.2 7.0 f hoco = 16 mhz note 3 , f ih = 16 mhz note 3 normal operation v dd = 3.6 v 3.1 5.0 v dd = 3.0 v 3.1 5.0 hs (high-speed main) mode note 5 f mx = 20 mhz note 2 , v dd = 3.6 v normal operation square wave input 3.5 5.9 ma resonator connection 3.6 6.0 f mx = 20 mhz note 2 , v dd = 3.0 v normal operation square wave input 3.5 5.9 resonator connection 3.6 6.0 f mx = 16 mhz note 2 , v dd = 3.6 v normal operation square wave input 2.9 4.5 resonator connection 3.1 4.6 f mx = 16 mhz note 2 , v dd = 3.0 v normal operation square wave input 2.9 4.5 resonator connection 3.1 4.6 f mx = 10 mhz note 2 , v dd = 3.6 v normal operation square wave input 2.1 3.5 resonator connection 2.2 3.5 f mx = 10 mhz note 2 , v dd = 3.0 v normal operation square wave input 2.1 3.5 resonator connection 2.2 3.5 hs (high-speed main) mode (pll operation) f pll = 48 mhz, f clk = 24 mhz note 2 normal operation v dd = 3.6 v 4.7 7.6 ma v dd = 3.0 v 4.7 7.6 f pll = 48 mhz, f clk = 12 mhz note 2 normal operation v dd = 3.6 v 3.1 5.2 v dd = 3.0 v 3.1 5.1 f pll = 48 mhz, f clk = 6 mhz note 2 normal operation v dd = 3.6 v 2.3 3.9 v dd = 3.0 v 2.3 3.9 subsystem clock operation f sub = 32.768 khz note 4 t a = -40c normal operation square wave input 4.6 6.9 ? a resonator connection 4.7 6.9 f sub = 32.768 khz note 4 t a = +25c normal operation square wave input 4.9 7.0 resonator connection 5.0 7.2 f sub = 32.768 khz note 4 t a = +50c normal operation square wave input 5.2 7.6 resonator connection 5.2 7.7 f sub = 32.768 khz note 4 t a = +70c normal operation square wave input 5.5 9.3 resonator connection 5.6 9.4 f sub = 32.768 khz note 4 t a = +85c normal operation square wave input 6.2 13.3 resonator connection 6.2 13.4 f sub = 32.768 khz note 4 t a = +105c normal operation square wave input 8.3 46.0 resonator connection 8.4 46.0
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 99 of 149 feb 21, 2014 note 1. total current flowing into v dd , including the input leakage current flowing when the level of the input pin is fixed to v dd , or v ss . the values below the max. column include the peripher al operation current. however, not including the current flowing into the lcd controller/driver, a/d converter, d/ a converter, comparator, lvd circuit, usb 2.0 function module, i/o port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. note 2. when high-speed on-chip oscillat or and subsystem clock are stopped. note 3. when high-speed system clock and subsystem clock are stopped. note 4. when high-speed on-chip oscillator and high-speed system clock are stopped. when amphs1 = 1 (ultra-low power consumption oscillation). however, not including the current fl owing into the real-time clock 2, 12-bit interval timer, and watchdog timer. note 5. relationship between operation voltage width, operation frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v ? v dd ? 3.6 v@1 mhz to 24 mhz 2.4 v ? v dd ? 3.6 v@1 mhz to 16 mhz remark 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or exter nal main system clock frequency) remark 2. f hoco : high-speed on-chip oscillator clock frequency (48 mhz max.) remark 3. f ih : main system clock source frequency when the high-speed on-chip oscillator clock divided 1, 2, 4, or 8, or the pll clock divided by 2, 4, or 8 is selected (24 mhz max.) remark 4. f sub : subsystem clock frequency (xt1 clock oscillation frequency) remark 5. except subsystem clock operation, temper ature condition of the typ. value is t a = 25c
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 100 of 149 feb 21, 2014 (notes and remarks are listed on the next page.) (t a = -40 to +105 c, 2.4 v ? v dd ? 3.6 v, v ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit supply current note 1 i dd2 note 2 halt mode hs (high-speed main) mode note 7 f hoco = 48 mhz note 4 , f ih = 24 mhz note 4 v dd = 3.6 v 0.77 3.4 ma v dd = 3.0 v 0.77 3.4 f hoco = 24 mhz note 4 , f ih = 24 mhz note 4 v dd = 3.6 v 0.55 2.7 v dd = 3.0 v 0.55 2.7 f hoco = 16 mhz note 4 , f ih = 16 mhz note 4 v dd = 3.6 v 0.48 1.9 v dd = 3.0 v 0.47 1.9 hs (high-speed main) mode note 7 f mx = 20 mhz note 3 , v dd = 3.6 v square wave input 0.35 2.10 ma resonator connection 0.51 2.20 f mx = 20 mhz note 3 , v dd = 3.0 v square wave input 0.34 2.10 resonator connection 0.51 2.20 f mx = 16 mhz note 3 , v dd = 3.6 v square wave input 0.30 1.25 resonator connection 0.45 1.41 f mx = 16 mhz note 3 , v dd = 3.0 v square wave input 0.29 1.23 resonator connection 0.45 1.41 f mx = 10 mhz note 3 , v dd = 3.6 v square wave input 0.23 1.10 resonator connection 0.30 1.20 f mx = 10 mhz note 3 , v dd = 3.0 v square wave input 0.22 1.10 resonator connection 0.30 1.20 hs (high-speed main) mode (pll operation) f mx = 48 mhz, f clk = 24 mhz note 3 v dd = 3.6 v 0.99 2.93 ma v dd = 3.0 v 0.99 2.92 f mx = 48 mhz, f clk = 12 mhz note 3 v dd = 3.6 v 0.89 2.51 v dd = 3.0 v 0.89 2.50 f mx = 48 mhz, f clk = 6 mhz note 3 v dd = 3.6 v 0.84 2.30 v dd = 3.0 v 0.84 2.29 subsystem clock operation f sub = 32.768 khz note 5 t a = -40c square wave input 0.32 0.61 ? a resonator connection 0.51 0.80 f sub = 32.768 khz note 5 t a = +25c square wave input 0.41 0.74 resonator connection 0.62 0.91 f sub = 32.768 khz note 5 t a = +50c square wave input 0.52 2.30 resonator connection 0.75 2.49 f sub = 32.768 khz note 5 t a = +70c square wave input 0.82 4.03 resonator connection 1.08 4.22 f sub = 32.768 khz note 5 t a = +85c square wave input 1.38 8.04 resonator connection 1.62 8.23 f sub = 32.768 khz note 5 t a = +105c square wave input 3.29 41.00 resonator connection 3.63 41.00 i dd3 note 6 stop mode note 8 t a = -40c 0.18 0.52 ? a t a = +25c 0.25 0.52 t a = +50c 0.34 2.21 t a = +70c 0.64 3.94 t a = +85c 1.18 7.95 t a = +105c 2.92 40.00
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 101 of 149 feb 21, 2014 note 1. total current flowing into v dd , including the input leakage current flowing wh en the level of the input pin is fixed to v dd or v ss . the values below the max. column include the peripher al operation current. however, not including the current flowing into the lcd controller/driver, a/d converter, d/ a converter, comparator, lvd circuit, usb 2.0 function module, i/o port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. note 2. during halt instruction ex ecution by flash memory. note 3. when high-speed on-chip oscillat or and subsystem clock are stopped. note 4. when high-speed system clock and subsystem clock are stopped. note 5. when high-speed on-chip oscillator and high-speed system cl ock are stopped. when rtclpc = 1 and setting ultra-low current consumption (amphs1 = 1). the current flowing into th e real-time clock 2 is included. however, not including the current flowing into the 12-bit interval timer and watchdog timer. note 6. not including the current flowing into the real-tim e clock 2, 12-bit interval timer, and watchdog timer. note 7. relationship between operation voltage width, operation frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v ? v dd ? 3.6 v@1 mhz to 24 mhz 2.4 v ? v dd ? 3.6 v@1 mhz to 16 mhz note 8. regarding the value for current to operate the subsystem clock in stop mode, refer to that in halt mode. remark 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or exter nal main system clock frequency) remark 2. f hoco : high-speed on-chip oscillator clock frequency (48 mhz max.) remark 3. f ih : main system clock source frequency when the high-speed on-chip oscillator clock divided 1, 2, 4, or 8, or the pll clock divided by 2, 4, or 8 is selected (24 mhz max.) remark 4. f sub : subsystem clock frequency (xt1 clock oscillation frequency) remark 5. except subsystem clock operation, temper ature condition of the typ. value is t a = 25c
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 102 of 149 feb 21, 2014 (notes and remarks are listed on the next page.) (t a = -40 to +105 c, 2.4 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit low-speed on-chip oscillator operating current i fil note 1 0.20 ? a rtc2 operating current i rtc notes 1, 3 0.02 ? a 12-bit interval timer operating current i tmka notes 1, 2, 4 0.02 ? a watchdog timer operating current i wdt notes 1, 4 f il = 15 khz 0.22 ? a a/d converter operating current i adc notes 6, 7 av dd = 3.0 v, when conversion at maximum speed 422 720 ? a av ref (+) current i avref note 8 av dd = 3.0 v, adrefp1 = 0, adrefp0 = 0 note 7 14.0 25.0 ? a av refp = 3.0 v, adrefp1 = 0, adrefp0 = 1 note 10 14.0 25.0 adrefp1 = 1, adrefp0 = 0 note 1 14.0 25.0 a/d converter reference voltage current i adref notes 1, 9 v dd = 3.0 v 75.0 ? a temperature sensor operating current i tmps note 1 78 ? a d/a converter operating current i dac notes 1, 11 per d/a converter channel 0.53 1.5 ma comparator operating current i cmp notes 1, 12 v dd = 3.6 v, regulator output voltage = 2.1 v window mode 12.5 ? a comparator high-speed mode 4.5 ? a comparator low-speed mode 1.2 ? a lvd operating current i lvi notes 1, 13 0.06 ? a self-programming operating current i fsp notes 1, 14 2.50 12.20 ma bgo operating current i bgo notes 1, 15 1.68 12.20 ma snooze operating current i snoz note 1 adc operation the mode is performed note 16 0.34 1.10 ma the a/d conversion operations are performed, low voltage mode, av refp = v dd = 3.0 v 0.53 2.04 csi/uart operation 0.70 1.54 ma lcd operating current i lcd1 notes 17, 18 external resistance division method f lcd = f sub lcd clock = 128 hz 1/3 bias 4-time slice v dd = 3.6 v, l v4 = 3.6 v 0.14 ? a i lcd2 note 17 internal voltage boosting method f lcd = f sub lcd clock = 128 hz 1/3 bias 4-time slice v dd = 3.0 v, l v4 = 3.0 v (vlcd = 04h) 0.61 ? a i lcd3 note 17 capacitor split method f lcd = f sub lcd clock = 128 hz 1/3 bias 4-time slice v dd = 3.0 v, l v4 = 3.0 v 0.12 ? a usb current note 19 i usb note 20 operating current during usb communication 4.88 ma i usb note 21 operating current in the usb suspended state 0.04 ma
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 103 of 149 feb 21, 2014 note 1. current flowing to v dd . note 2. when high speed on-chip oscillator and high-speed system clock are stopped. note 3. current flowing only to the real-time cl ock 2 (excluding the operating current of the low-speed on-chip oscillator and the xt1 oscillator). the supply current of the rl78 microcontrollers is the sum of the values of either i dd1 or i dd2 , and i rtc , when the real-time clock 2 operates in operation mode or halt mode. when the low-speed on-chip oscillator is selected, i fil should be added. i dd2 subsystem clock operation includes the operational current of the real-time clock 2. note 4. current flowing only to the 12-bit interv al timer (excluding the operating current of the low-speed on-chip oscillator and the xt1 oscillator). the supply current of the rl78 micr ocontrollers is the sum of the values of either i dd1 or i dd2 , and i tmka , when the 12-bit interval timer operates in operation m ode or halt mode. when the low-speed on-chip oscillator is selected, i fil should be added. i dd2 subsystem clock operation includes the operational current of the 12-bit interval timer. note 5. current flowing only to the watchdog time r (including the operating current of the low-speed on-chip oscillator). the current value of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i wdt when the watchdog timer operates in stop mode. note 6. current flowing only to the a/d conver ter. the supply current of the rl78 microcontrollers is the sum of i dd1 or i dd2 and i adc , i avref , i adref when the a/d converter operates in an operation mode or the halt mode. note 7. current flowing to the av dd . note 8. current flowing from the reference voltage source of a/d converter. note 9. operation current flowing to the internal reference voltage. note 10. current flowing to the av refp . note 11. current flowing only to the d/a converter. the current value of the rl78 microcontrollers is the sum of i dd1 or i dd2 and i da when the d/a converter operates in an operation mode or the halt mode. note 12. current flowing only to the comparator circuit. the curr ent value of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i cmp when the comparator circuit operates in the operating, halt or stop mode. note 13. current flowing only to the lvd circuit. the current va lue of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i lvi when the lvd circuit operates in the operating, halt or stop mode. note 14. current flowing only during self-programming. note 15. current flowing only during data flash rewrite. note 16. for shift time to the snooze mode, see 23.3.3 snooze mode in the rl78/l1c user?s manual. note 17. current flowing only to t he lcd controller/driver (v dd pin). the current value of the rl78 microcontrollers is the sum of the lcd operating current (i lcd1 , i lcd2 or i lcd3 ) to the supply current (i dd1 , or i dd2 ) when the lcd controller/driver operates in an operation mode or halt mode. not in cluding the current that flows through the lcd panel. note 18. not including the current that flows through t he external divider resistor divider resistor. note 19. current flowing to the uv bus . note 20. including the operating current when f pll = 48 mhz. note 21. including the current supplied from the pu ll-up resistor of the udp pin to the pu ll-down resistor of the host device, in addition to the current consumed by this mcu during the suspended state. remark 1. f il : low-speed on-chip oscillator clock frequency remark 2. f sub : subsystem clock frequency (x t1 clock oscillation frequency) remark 3. f clk : cpu/peripheral hardware clock frequency remark 4. temperature condition of the typ. value is t a = 25c
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 104 of 149 feb 21, 2014 3.4 ac characteristics 3.4.1 basic operation remark f mck : timer array unit operation clock frequency (operation clock to be set by the cksmn bit of timer mode register mn (tmrmn). m: unit number (m = 0), n: channel number (n = 0 to 7)) (t a = -40 to +105 c, 2.4 v ? av dd = v dd ? 3.6 v, v ss = 0 v) (1/2) items symbol conditions min. typ. max. unit instruction cycle (minimum instruction execution time) t cy main system clock (f main ) operation hs (high-speed main) mode 2.7 v ? v dd ? 3.6 v 0.0417 1 ? s 2.4 v ? v dd < 2.7 v 0.0625 1 ? s subsystem clock (f sub ) operation 2.4 v ? v dd ? 3.6 v 28.5 30.5 31.3 ? s in the self- programming mode hs (high-speed main) mode 2.7 v ? v dd ? 3.6 v 0.0417 1 ? s 2.4 v ? v dd < 2.7 v 0.0625 1 ? s external main system clock frequency f ex 2.7 v ? v dd ? 3.6 v 1.0 20.0 mhz 2.4 v ? v dd < 2.7 v 1.0 16.0 mhz f ext 32 35 khz external main system clock input high-level width, low-level width t exh , t exl 2.7 v ? v dd ? 3.6 v 24 ns 2.4 v ? v dd < 2.7 v 30 ns t exhs , t exls 13.7 ? s ti00 to ti07 input high-level width, low-level width t tih , t til 1/f mck + 10 ns
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 105 of 149 feb 21, 2014 (t a = -40 to +105 c, 2.4 v ? av dd = v dd ? 3.6 v, v ss = 0 v) (2/2) items symbol conditions min. typ. max. unit to00 to to07, tkbo00, tkbo01, tkbo10, tkbo11, tkbo20, tkbo21 output frequency f to hs (high-speed main) mode 2.7 v ? v dd ? 3.6 v 8 mhz 2.4 v ? v dd < 2.7 v 8 mhz pclbuz0, pclbuz1 output frequency f pcl hs (high-speed main) mode 2.7 v ? v dd ? 3.6 v 8 mhz 2.4 v ? v dd < 2.7 v 8 mhz interrupt input high-level width, low-level width t inth , t intl intp0 to intp7 2.4 v ? v dd ? 3.6 v 1 ? s key interrupt input low-level width t kr 2.4 v ? v dd ? 3.6 v 250 ns tmkb2 forced output stop input high-level width t ihr intp0 to intp7 f clk ? 16 mhz 125 ns f clk ? 16 mhz 2 f clk reset low-level width t rsl 10 ? s
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 106 of 149 feb 21, 2014 minimum instruction execution time during main system clock operation t cy vs v dd (hs (high-speed main) mode) 1.0 0.1 0 10 1.0 2.0 3.0 4.0 3.6 2.7 0.01 2.4 0.0417 0.0625 0.05 during self programming when high-speed system clock is selected when the high-speed on-chip oscillator clock is selected cycle time t cy [s] supply voltage v dd [v]
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 107 of 149 feb 21, 2014 ac timing test points external system clock timing ti/to timing interrupt request input timing v ih /v oh v il /v ol v ih /v oh test points v il /v ol exclk/exclks 1/f ex 1/f exs t exl t exls t exh t exhs t til t tih 1/f to ti00 to ti07, ti10 to ti17 to00 to to07, to10 to to17, tkbo00, tkbo01, tkbo10, tkbo11, tkbo20, tkbo21 intp0 to intp7 t intl t inth
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 108 of 149 feb 21, 2014 key interrupt input timing timer kb2 input timing reset input timing t kr kr0 to kr7 intp0 to intp7 t ihr t rsl reset
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 109 of 149 feb 21, 2014 3.5 peripheral functions characteristics 3.5.1 serial array unit note 1. transfer rate in the snooze mode is 4800 bps only. note 2. the following conditions are required for low voltage interface. 2.4 v ? v dd < 2.7 v: max. 1.3 mbps note 3. the maximum operating frequencies of the cpu/peripheral hardware clock (f clk ) are: hs (high-speed main) mode: 24 mhz (2.7 v ? v dd ? 3.6 v) 16 mhz (2.4 v ? v dd ? 3.6 v) caution select the normal input buffer for the rxdq pin and the normal output mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). uart mode connection diagram (durin g communication at same potential) uart mode bit width (durin g communication at same potential) (reference) remark 1. q: uart number (q = 0 to 3), g: pim and pom number (g = 0 to 3) remark 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13)) (1) during communication at same potential (uart mode) (t a = -40 to +105 c, 2.4 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode unit min. max. transfer rate note 1 2.4 v ? v dd ? 3.6 v f mck /12 note 2 bps theoretical value of the maximum transfer rate f mck = f clk note 3 2.0 mbps v ih /v oh v il /v ol v ih /v oh test points v il /v ol txdq rxdq user?s device rx tx rl78 microcontroller baud rate error tolerance txdq rxdq high-/low-bit width 1/transfer rate
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 110 of 149 feb 21, 2014 note 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 4. c is the load capacitance of the sckp and sop output lines. caution select the normal input buffer for the sip pin and the normal output mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). remark 1. p: csi number (p = 00, 10, 20, 30), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim number (g = 0 to 3) remark 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13)) (2) during communication at same potential (csi mo de) (master mode, sckp... internal clock output) (t a = -40 to +105 c, 2.4 v d v dd d 3.6 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode unit min. max. sckp cycle time t kcy1 t kcy1 t f clk /4 2.7 v d v dd d 3.6 v 250 ns 2.4 v d v dd d 3.6 v 500 ns sckp high-/low-level width t kh1 , t kl1 2.7 v d v dd d 3.6 v t kcy1 /2 - 36 ns 2.4 v d v dd d 3.6 v t kcy1 /2 - 76 ns sip setup time (to sckp ) note 1 t sik1 2.7 v d v dd d 3.6 v 66 ns 2.4 v d v dd d 3.6 v 133 ns sip hold time (from sckp ) note 2 t ksi1 38 ns delay time from sckp to sop output note 3 t kso1 c = 30 pf note 4 50 ns
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 111 of 149 feb 21, 2014 note 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 4. c is the load capacitance of the sop output lines. note 5. the maximum transfer rate when using the snooze mode is 1 mbps. caution select the normal input buffer for the sip pin and the normal output mode for the sop pin by using port input mode register g (pimg) and port output mode register g (pomg). remark 1. p: csi number (p = 00, 10, 20, 30), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim number (g = 0 to 3) remark 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13)) (3) during communication at same potential (csi mode) (slave mode, sckp... external clock input) (t a = -40 to +105 c, 2.4 v d v dd d 3.6 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode unit min. max. sckp cycle time note 5 t kcy2 2.7 v d v dd 3.6 v f mck ! 16 mhz 16/f mck ns f mck d 16 mhz 12/f mck ns 2.4 v d v dd 3.6 v 12/f mck and 1000 ns sckp high-/low-level width t kh2 , t kl2 2.7 v d v dd d 3.6 v t kcy2 /2 - 16 ns 2.4 v d v dd d 3.6 v t kcy2 /2 - 36 ns sip setup time (to sckp ) note 1 t sik2 2.7 v d v dd d 3.6 v 1/f mck + 40 ns 2.4 v d v dd d 3.6 v 1/f mck + 60 ns sip hold time (from sckp ) note 2 t ksi2 1/f mck + 62 ns delay time from sckp to sop output note 3 t kso2 c = 30 pf note 4 2.7 v d v dd d 3.6 v 2/f mck + 66 ns 2.4 v d v dd 3.6 v 2/f mck + 113 ns
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 112 of 149 feb 21, 2014 csi mode connection diagram (during communication at same potential) remark 1. p: csi number (p = 00, 10, 20, 30) remark 2. m: unit number, n: channel number (mn = 00 to 03, 10 to 13) sckp sop user's device sck si sip so rl78 microcontroller
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 113 of 149 feb 21, 2014 csi mode serial transfer timing (d uring communication at same potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) csi mode serial transfer timing (d uring communication at same potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) remark 1. p: csi number (p = 00, 10, 20, 30) remark 2. m: unit number, n: channel number (mn = 00 to 03, 10 to 13) sip sop t kcy1, 2 input data output data sckp t kl1, 2 t kh1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 input data output data t kcy1, 2 t kh1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 sip sop sckp t kl1, 2
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 114 of 149 feb 21, 2014 note 1. the value must also be equal to or less than f mck /4. note 2. set the f mck value to keep the hold time of sclr = ?l? and sclr = ?h?. caution select the normal input buffer and the n-ch open drain output (v dd tolerance) mode for the sdar pin and the normal output mode for the sclr pin by using port input mode register g (pimg) and port output mode register h (pomh). simplified i 2 c mode connection diagram (during communication at same potential) (4) during communication at sa me potential (simplified i 2 c mode) (t a = -40 to +105 c, 2.4 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode unit min. max. sclr clock frequency f scl 2.7 v ? v dd ? 3.6 v, c b = 50 pf, r b = 2.7 k ? 400 note 1 khz 2.4 v ? v dd ? 3.6 v, c b = 100 pf, r b = 3 k ? 100 note 1 khz hold time when sclr = ?l? t low 2.7 v ? v dd ? 3.6 v, c b = 50 pf, r b = 2.7 k ? 1200 ns 2.4 v ? v dd ? 3.6 v, c b = 100 pf, r b = 3 k ? 4600 ns hold time when sclr = ?h? t high 2.7 v ? v dd ? 3.6 v, c b = 50 pf, r b = 2.7 k ? 1200 ns 2.4 v ? v dd ? 3.6 v, c b = 100 pf, r b = 3 k ? 4600 ns data setup time (reception) t su: dat 2.7 v ? v dd ? 3.6 v, c b = 50 pf, r b = 2.7 k ? 1/f mck + 200 note 2 ns 2.4 v ? v dd ? 3.6 v, c b = 100 pf, r b = 3 k ? 1/f mck + 580 note 2 ns data hold time (transmission) t hd: dat 2.7 v ? v dd ? 3.6 v, c b = 50 pf, r b = 2.7 k ? 0 770 ns 2.4 v ? v dd ? 3.6 v, c b = 100 pf, r b = 3 k ? 0 1420 ns sdar sclr user?s device sda scl v dd r b rl78 microcontroller
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 115 of 149 feb 21, 2014 simplified i 2 c mode serial transfer timing (d uring communication at same potential) remark 1. r b [ ? ]: communication line (sdar) pull-up resistance, c b [f]: communication line (sdar, sclr) load capacitance remark 2. r: iic number (r = 00, 10, 20, 30), g: pim number (g = 0 to 3), h: pom number (h = 0 to 3) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mo de register mn (smrmn). m: unit number (m = 0, 1), n: channel number (n = 0, 2), mn = 00 to 03, 10 to 13) sdar sclr 1/f scl t low t high t su: dat t hd: dat
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 116 of 149 feb 21, 2014 note 1. transfer rate in the snooze mode is 4,800 bps only. note 2. use it with v dd ? vb. note 3. the following conditions are required for low voltage interface. 2.4 v ? v dd ? 2.7 v: max. 2.6 mbps note 4. the maximum operating frequencies of the cpu/peripheral hardware clock (f clk ) are: hs (high-speed main) mode: 24 mhz (2.7 v ? v dd ? 3.6 v) 16 mhz (2.4 v ? v dd ? 3.6 v) caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance) mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. remark 1. v b [v]: communication line voltage remark 2. q: uart number (q = 0 to 3), g: pim and pom number (g = 0 to 3) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13) (5) communication at different pote ntial (1.8 v, 2.5 v) (uart mode) (t a = -40 to +105 c, 2.4 v ? v dd ? 3.6 v, v ss = 0 v) (1/2) parameter symbol conditions hs (high-speed main) mode unit min. max. transfer rate notes 1, 2 reception 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v f mck /12 note 1 bps theoretical value of the maximum transfer rate f mck = f clk note 4 2.0 mbps 1.8 v ? v dd ? 3.3 v, 1.6 v ? v b ? 2.0 v f mck /12 notes 1, 2, 3 bps theoretical value of the maximum transfer rate f mck = f clk note 4 1.3 mbps
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 117 of 149 feb 21, 2014 note 1. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 2.7 v ? v dd < 3.6 v and 2.3 v ? v b ? 2.7 v note 2. this value as an example is calculated when the c onditions described in the ?conditions? column are met. refer to note 1 above to calculate the maximum tr ansfer rate under conditions of the customer. note 3. use it with v dd ? v b . note 4. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 2.4 v ? v dd < 3.3 v and 1.6 v ? v b ? 2.0 v note 5. this value as an example is calculated when the c onditions described in the ?conditions? column are met. refer to note 4 above to calculate the maximum tr ansfer rate under conditions of the customer. caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance) mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. (5) communication at different pote ntial (1.8 v, 2.5v) (uart mode) (t a = -40 to +105 c, 2.4 ? v dd ? 3.6 v, v ss = 0 v) (2/2) parameter symbol conditions hs (high-speed main) mode unit min. max. transfer rate note 2 transmission 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v note 1 bps theoretical value of the maximum transfer rate c b = 50 pf, r b = 2.7 k ? , v b = 2.3 v 1.2 note 2 mbps 1.8 v ? v dd ? 3.3 v, 1.6 v ? v b ? 2.0 v notes 3, 4 bps theoretical value of the maximum transfer rate c b = 50 pf, r b = 5.5 k ? , v b = 1.6 v 0.43 note 5 mbps maximum transfer rate = 1 [bps] baud rate error (theoretical value) = 1 transfer rate ? 2 - {-c b ? r b ? in (1 - )} ? 3 {-c b ? r b ? in (1 - )} ( ) ? number of transferred bits 1 transfer rate ? 100 [%] * this value is the theoretical value of the relative difference between the transmission and reception sides . 2.0 v b 2.0 v b maximum transfer rate = 1 [bps] baud rate error (theoretical value) = 1 transfer rate ? 2 - {-c b ? r b ? in (1 - )} ? 3 {-c b ? r b ? in (1 - )} ( ) ? number of transferred bits 1 transfer rate ? 100 [%] * this value is the theoretical value of the relative difference between the transmission and reception sides . 1.5 v b 1.5 v b
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 118 of 149 feb 21, 2014 uart mode connection diagram (during communication at different potential) uart mode bit width (during communicatio n at different potential) (reference) remark 1. r b [ ? ]: communication line (txdq) pull-up resistance, c b [f]: communication line (txdq) load capacitance, v b [v]: communication line voltage remark 2. q: uart number (q = 0 to 3), g: pim and pom number (g = 0 to 3) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10 to 13)) txdq rxdq user?s device rx tx v b r b rl78 microcontroller baud rate error tolerance high-/low-bit width 1/transfer rate baud rate error tolerance high-bit width low-bit width 1/transfer rate txdq rxdq
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 119 of 149 feb 21, 2014 note use it with v dd ? v b . caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance) mode for the sop pin and sckp pin by using port input mode register g (p img) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. (remarks are listed on the page after the next page.) (6) communication at differe nt potential (1.8 v, 2.5 v) (csi mode ) (master mode, sckp... internal clock output) (t a = -40 to +105 c, 2.4 v ? v dd ? 3.6 v, v ss = 0 v) (1/2) parameter symbol conditions hs (high-speed main) mode unit min. max. sckp cycle time t kcy1 t kcy1 ? f clk /4 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 1000 note ns 2.4 v ? v dd ? 3.3 v, 1.6 v ? v b ? 1.8 v, c b = 30 pf, r b = 5.5 k ? 2300 note ns sckp high-level width t kh1 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? t kcy1 /2 - 340 ns 2.4 v ? v dd ? 3.3 v, 1.6 v ? v b ? 2.0 v, c b = 30 pf, r b = 5.5 k ? t kcy1 /2 - 916 ns sckp low-level width t kl1 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? t kcy1 /2 - 36 ns 2.4 v ? v dd ? 3.3 v, 1.6 v ? v b ? 2.0 v, c b = 30 pf, r b = 5.5 k ? t kcy1 /2 - 100 ns
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 120 of 149 feb 21, 2014 note 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. note 2. when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 3. use it with v dd ? v b . caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance) mode for the sop pin and sckp pin by using port input mode register g (p img) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. (remarks are listed on the next page.) (6) communication at differe nt potential (1.8 v, 2.5 v) (csi mode ) (master mode, sckp... internal clock output) (t a = -40 to +105 c, 2.4 v ? v dd ? 3.6 v, v ss = 0 v) (2/2) parameter symbol conditions hs (high-speed main) mode unit min. max. sip setup time (to sckp 9) note 1 t sik1 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 354 ns 2.4 v ? v dd ? 3.3 v, 1.6 v ? v b ? 2.0 v note 3 , c b = 30 pf, r b = 5.5 k ? 958 ns sip hold time (from sckp 9) note 1 t ksi1 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 38 ns 2.4 v ? v dd ? 3.3 v, 1.6 v ? v b ? 2.0 v note 3 , c b = 30 pf, r b = 5.5 k ? 38 ns delay time from sckp ; to sop output note 1 t kso1 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 390 ns 2.4 v ? v dd ? 3.3 v, 1.6 v ? v b ? 2.0 v note 3 , c b = 30 pf, r b = 5.5 k ? 966 ns sip setup time (to sckp ;) note 2 t sik1 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 88 ns 2.4 v ? v dd ? 3.3 v, 1.6 v ? v b ? 2.0 v note 3 , c b = 30 pf, r b = 5.5 k ? 220 ns sip hold time (from sckp ;) note 2 t ksi1 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 38 ns 2.4 v ? v dd ? 3.3 v, 1.6 v ? v b ? 2.0 v note 3 , c b = 30 pf, r b = 5.5 k ? 38 ns delay time from sckp 9 to sop output note 2 t kso1 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v, c b = 30 pf, r b = 2.7 k ? 50 ns 2.4 v ? v dd ? 3.3 v, 1.6 v ? v b ? 2.0 v note 3 , c b = 30 pf, r b = 5.5 k ? 50 ns
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 121 of 149 feb 21, 2014 csi mode connection diagram (during communication at different potential) remark 1. r b [ ? ]: communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sckp, sop) load capacitance, v b [v]: communication line voltage remark 2. p: csi number (p = 00, 10, 20, 30), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim and pom number (g = 0 to 3) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) sckp sop user?s device sck si sip so v b r b v b r b rl78 microcontroller
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 122 of 149 feb 21, 2014 csi mode serial transfer timing (master mode ) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) csi mode serial transfer timing (master mode ) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) remark p: csi number (p = 00, 10, 20, 30), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim and pom number (g = 0 to 3) input data sip sop t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 output data sckp input data output data sip sop sckp t kcy1 t kh1 t kl1 t sik1 t ksi1 t kso1
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 123 of 149 feb 21, 2014 (notes and caution are listed on the next page. remarks are listed on the page after the next page.) (7) communication at different potential (1.8 v, 2.5 v) (csi mode) (slave mode, sckp... external clock input) (t a = -40 to +105 c, 2.4 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode unit min. max. sckp cycle time note 1 t kcy2 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v 20 mhz ? f mck ? 24 mhz 32/f mck ns 16 mhz ? f mck ? 20 mhz 28/f mck ns 8 mhz ? f mck ? 16 mhz 24/f mck ns 4 mhz ? f mck ? 8 mhz 16/f mck ns f mck ? 4 mhz 12/f mck ns 2.4 v ? v dd < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 20 mhz ? f mck ? 24 mhz 72/f mck ns 16 mhz ? f mck ? 20 mhz 64/f mck ns 8 mhz ? f mck ? 16 mhz 52/f mck ns 4 mhz ? f mck ? 8 mhz 32/f mck ns f mck ? 4 mhz 20/f mck ns sckp high-/low-level width t kh2 , t kl2 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v t kcy2 /2 - 36 ns 2.4 v ? v dd < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 t kcy2 /2 - 100 ns sip setup time (to sckp 9) note 3 t sik2 2.7 v ? v dd ? 3.6 v 1/f mck + 40 ns 2.4 v ? v dd < 3.3 v 1/f mck + 60 ns sip hold time (from sckp 9) note 4 t ksi2 1/f mck + 62 ns delay time from sckp ; to sop output note 5 t kso2 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v c b = 30 pf, r b = 2.7 k ? 2/f mck + 428 ns 2.4 v ? v dd < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 c b = 30 pf, r b = 5.5 k ? 2/f mck + 1146 ns
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 124 of 149 feb 21, 2014 note 1. transfer rate in the snooze mode: max. 1 mbps note 2. use it with v dd ? v b . note 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ; ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 4. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ; ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. note 5. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp 9 ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. caution select the ttl input buffer for the sip pin and sckp pin and the n-ch open drain output (v dd tolerance) mode for the sop pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. (remarks are listed on the next page.)
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 125 of 149 feb 21, 2014 csi mode connection diagram (during communication at different potential) remark 1. r b [ ? ]: communication line (sop) pull-up resistance, c b [f]: communication line (sop) load capacitance, v b [v]: communication line voltage remark 2. p: csi number (p = 00, 10, 20, 30), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim and pom number (g = 0 to 3) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00, 02, 10, 12)) sckp sop user?s device sck si sip so v b r b rl78 microcontroller
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 126 of 149 feb 21, 2014 csi mode serial transfer timing (slave mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) csi mode serial transfer timing (slave mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) remark p: csi number (p = 00, 10, 20, 30), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim and pom number (g = 0 to 3) sip sop sckp input data output data t kcy2 t kh2 t kl2 t sik2 t ksi2 t kso2 input data output data sip sop sckp t kcy2 t kl2 t kh2 t sik2 t ksi2 t kso2
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 127 of 149 feb 21, 2014 note 1. the value must also be equal to or less than f mck /4. note 2. use it with v dd ? v b . note 3. set the f mck value to keep the hold time of sclr = ?l? and sclr = ?h?. caution select the ttl input buffer and the n-ch open drain output (v dd tolerance) mode for the sdar pin and the n-ch open drain output (v dd tolerance) mode for the sclr pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. (remarks are listed on the next page.) (8) communication at different potent ial (1.8 v, 2.5 v) (simplified i 2 c mode) (t a = -40 to +105 c, 2.4 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode unit min. max. sclr clock frequency f scl 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v, c b = 50 pf, r b = 2.7 k ? 400 note 1 khz 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v, c b = 100 pf, r b = 2.7 k ? 100 note 1 khz 2.4 v ? v dd < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 , c b = 100 pf, r b = 5.5 k ? 100 note 1 khz hold time when sclr = ?l? t low 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b ? 2.7 v, c b = 50 pf, r b = 2.7 k ? 1200 ns 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b <2.7 v, c b = 100 pf, r b = 2.7 k ? 4600 ns 2.4 v ? v dd < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 , c b = 100 pf, r b = 5.5 k ? 4650 ns hold time when sclr = ?h? t high 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b < 2.7 v, c b = 50 pf, r b = 2.7 k ? 500 ns 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b < 2.7 v, c b = 100 pf, r b = 2.7 k ? 2400 ns 2.4 v ? v dd < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 , c b = 100 pf, r b = 5.5 k ? 1830 ns data setup time (reception) t su:dat 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b < 2.7 v, c b = 50 pf, r b = 2.7 k ? 1/f mck + 340 note 3 ns 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b < 2.7 v, c b = 100 pf, r b = 2.7 k ? 1/f mck + 760 note 3 ns 2.4 v ? v dd < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 , c b = 100 pf, r b = 5.5 k ? 1/f mck + 570 note 3 ns data hold time (transmission) t hd:dat 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b < 2.7 v, c b = 50 pf, r b = 2.7 k ? 0 770 ns 2.7 v ? v dd ? 3.6 v, 2.3 v ? v b < 2.7 v, c b = 100 pf, r b = 2.7 k ? 0 1420 ns 2.4 v ? v dd < 3.3 v, 1.6 v ? v b ? 2.0 v note 2 , c b = 100 pf, r b = 5.5 k ? 0 1215 ns
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 128 of 149 feb 21, 2014 simplified i 2 c mode connection diagram (during communication at different potential) simplified i 2 c mode serial transfer timing (durin g communication at different potential) remark 1. r b [ ? ]: communication line (sdar, sclr) pull-up resistance, c b [f]: communication line (sdar, sclr) load capacitance, v b [v]: communication line voltage remark 2. r: iic number (r = 00, 10, 20, 30), g: pim, pom number (g = 0 to 3) remark 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mo de register mn (smrmn). m: unit number (m = 0, 1), n: channel number (n = 0, 2), mn = 00, 02, 10, 12) sdar sclr user?s device sda scl v b r b v b r b rl78 microcontroller sdar sclr 1/f scl t low t high t su: dat t hd: dat
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 129 of 149 feb 21, 2014 3.5.2 serial interface iica note 1. the first clock pulse is generat ed after this period when the star t/restart condition is detected. note 2. the maximum value (max.) of t hd:dat is during normal transfer and a wait state is inserted in the ack (acknowledge) timing. remark the maximum value of c b (communication line capacitance) and the value of r b (communication line pull-up resistor) at that time in each mode are as follows. standard mode: c b = 400 pf, r b = 2.7 k ? fast mode: c b = 320 pf, r b = 1.1 k ? iica serial transfer timing (t a = -40 to +105 c, 2.4 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions hs (high-speed main) mode unit standard mode fast mode min. max. min. max. scla0 clock frequency f scl fast mode: f clk ? 3.5 mhz ? ? 0 400 khz standard mode: f clk ? 1 mhz 0 100 ? ? khz setup time of restart condition t su: sta 4.7 0.6 ? s hold time note 1 t hd: sta 4.0 0.6 ? s hold time when scla0 = ?l? t low 4.7 1.3 ? s hold time when scla0 = ?h? t high 4.0 0.6 ? s data setup time (reception) t su: dat 250 100 ns data hold time (transmission) note 2 t hd: dat 03.450 0.9 ? s setup time of stop condition t su: sto 4.0 0.6 ? s bus-free time t buf 4.7 1.3 ? s t su: dat t hd: sta restart condition scln sdan t low t high t su: sta t hd: sta t su: sto stop condition stop condition start condition t hd: dat t buf
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 130 of 149 feb 21, 2014 3.5.3 usb note value of instantaneous voltage note excludes the first signal transition from the idle state. (1) electrical specifications (t a = -40 to +105 c, 2.4 v ? v dd ? 3.6 v, v ss = 0 v, hs (high-speed main) mode only) parameter symbol conditions min. typ. max. unit u regc u regc output voltage characteristic u regc uv bus = 4.0 to 5.5 v, pxxcon = vddusbe = 1 3.0 3.3 3.6 v uv bus uv bus input voltage characteristic uv bus function 4.35 (4.02 note ) 5.00 5.25 v (t a = -40 to +105 c, 4.35 v ? uv bus ? 5.25 v, 2.4 v ? v dd ? 3.6 v, v ss = 0 v, hs (high-speed main) mode only) parameter symbol conditions min. typ. max. unit input characteristic (fs/ls receiver) input voltage v ih 2.0 v v il 0.8 v difference input sensitivity v di | udp voltage - udm voltage | 0.2 v difference common mode range v cm 0.8 2.5 v output characteristic (fs driver) output voltage v oh i oh = -200 ? a2 . 8 3 . 6 v v ol i ol = 2 ma 0 0.3 v transition time rising t fr rising: from 10% to 90% of amplitude, falling: from 90% to 10% of amplitude, cl = 50 pf 420ns falling t ff 42 0n s matching (tfr/tff) v frfm 90 111.1 % crossover voltage v fcrs 1.3 2.0 v output impedance z drv 28 44 ? output characteristic (ls driver) output voltage v oh 2.8 3.6 v v ol 00 . 3v transition time rising t lr rising: from 10% to 90% of amplitude, falling: from 90% to 10% of amplitude, cl = 250 pf to 750 pf the udp and udm pins ar e individually pulled down via 15 k ? 75 300 ns falling t lf 75 300 ns matching (tfr/tff) note v ltfm 80 125 % crossover voltage note v lcrs 1.3 2.0 v pull-up, pull-down pull-down resistor r pd 14.25 24.80 k ? pull-up resistor idle r pui 0.9 1.575 k ? reception r pua 1.425 3.09 k ? uv bus uv bus pull-down resistor r vbus uv bus voltage = 5.5 v 1000 k ? uv bus input voltage v ih 3.20 v v il 0.8 v
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 131 of 149 feb 21, 2014 timing of udp and udm (2) bc standard (t a = -40 to +105 c, 4.35 v ? uv bus ? 5.25 v, 2.4 v ? v dd ? 3.6 v, v ss = 0 v, hs (high-speed main) mode only) parameter symbol conditions min. typ. max. unit usb standard bc1.2 udp sink current i dp_sink 25 100 175 ? a udm sink current i dm_sink 25 100 175 ? a dcd source current i dp_src 71013 ? a data detection voltage v dat_ref 0.25 0.325 0.4 v udp source voltage v dp_src output current 250 ? a 0.5 0.6 0.7 v udm source voltage v dm_src output current 250 ? a 0.5 0.6 0.7 v udp udm 10% v crs (crossover voltage) 90% 90% 10% t r t f
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 132 of 149 feb 21, 2014 (3) bc option standard (t a = -40 to +105 c, 4.35 v ? uv bus ? 5.25 v, 2.4 v ? v dd ? 3.6, v ss = 0 v) parameter symbol conditions min. typ. max. unit udp/udm input reference voltage (uv bus divider ratio) (function) vdseli [3: 0] (i = 0, 1) 0000 v ddet0 27 32 37 %uvbus 0001 v ddet1 29 34 39 %uvbus 0010 v ddet2 32 37 42 %uvbus 0011 v ddet3 35 40 45 %uvbus 0100 v ddet4 38 43 48 %uvbus 0101 v ddet5 41 46 51 %uvbus 0110 v ddet6 44 49 54 %uvbus 0111 v ddet7 47 52 57 %uvbus 1000 v ddet8 51 56 61 %uvbus 1001 v ddet9 55 60 65 %uvbus 1010 v ddet10 59 64 69 %uvbus 1011 v ddet11 63 68 73 %uvbus 1100 v ddet12 67 72 73 %uvbus 1101 v ddet13 71 76 81 %uvbus 1110 v ddet14 75 80 85 %uvbus 1111 vd det15 79 84 89 %uvbus
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 133 of 149 feb 21, 2014 3.6 analog characteristics 3.6.1 a/d converte r characteristics note excludes quantization error ( ? 1/2 lsb). caution always use av dd pin with the same potential as the v dd pin. classification of a/d converter characteristics reference voltage input channel reference voltage (+) = av refp reference voltage (-) = av refm reference voltage (+) = av dd reference voltage (-) = av ss reference voltage (+) = internal reference voltage reference voltage (-) = av ss high-accuracy channel; ani0 to ani6 (input buffer power supply: av dd ) refer to 3.6.1 (1) .r e f e r t o 3.6.1 (2) . refer to 3.6.1 (5) . standard channel; ani16 to ani21 (input buffer power supply: v dd ) refer to 3.6.1 (3) .r e f e r t o 3.6.1 (4) . internal reference voltage, temperature sensor output voltage refer to 3.6.1 (3) .r e f e r t o 3.6.1 (4) .? (1) when reference voltage (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage (-) = av refm /ani1 (adrefm = 1), conver sion target: ani2 to ani6 (t a = -40 to +105 c, 2.4 v ? av refp ? av dd = v dd ? 3.6 v, v ss = 0 v, av ss = 0 v, reference voltage (+) = av refp , reference voltage (-) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 2.4 v ? av refp ? av dd ? 3.6 v 8 12 bit overall error note ainl 12-bit resolution 2.4 v ? av refp ? av dd ? 3.6 v ? 6.0 lsb conversion time t conv adtyp = 0, 12-bit resolution 2.4 v ? av refp ? av dd ? 3.6 v 3.375 ? s zero-scale error note e zs 12-bit resolution 2.4 v ? av refp ? av dd ? 3.6 v ? 4.5 lsb full-scale error note e fs 12-bit resolution 2.4 v ? av refp ? av dd ? 3.6 v ? 4.5 lsb integral linearity error note ile 12-bit resolution 2.4 v ? av refp ? av dd ? 3.6 v ? 2.0 lsb differential linearity error note dle 12-bit resolution 2.4 v ? av refp ? av dd ? 3.6 v ? 1.5 lsb analog input voltage v ain 0a v refp v
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 134 of 149 feb 21, 2014 note excludes quantization error ( ? 1/2 lsb). caution always use av dd pin with the same potential as the v dd pin. (2) when reference voltage (+) = av dd (adrefp1 = 0, adrefp0 = 0), reference voltage (-) = av ss (adrefm = 0), conversion target: ani0 to ani6 (t a = -40 to +105 c, 2.4 v ? av dd = v dd ? 3.6 v, v ss = 0 v, av ss = 0 v, reference voltage (+) = av dd , reference voltage (-) = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 2.4 v ? av dd ? 3.6 v 8 12 bit overall error note ainl 12-bit resolution 2.4 v ? av dd ? 3.6 v ? 7.5 lsb conversion time t conv adtyp = 0, 12-bit resolution 2.4 v ? av dd ? 3.6 v 3.375 ? s zero-scale error note e zs 12-bit resolution 2.4 v ? av dd ? 3.6 v ? 6.0 lsb full-scale error note e fs 12-bit resolution 2.4 v ? av dd ? 3.6 v ? 6.0 lsb integral linearity error note ile 12-bit resolution 2.4 v ? av dd ? 3.6 v ? 3.0 lsb differential linearity error note dle 12-bit resolution 2.4 v ? av dd ? 3.6 v ? 2.0 lsb analog input voltage v ain 0a v dd v
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 135 of 149 feb 21, 2014 note 1. excludes quantization error ( ? 1/2 lsb). note 2. refer to 3.6.2 temperature sensor, internal reference voltage output characteristics . caution always use av dd pin with the same potential as the v dd pin. (3) when reference voltage (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage (-) = av refm /ani1 (adrefm = 1), conversion target ani16 to ani21, internal reference voltage, temperature sensor output voltage (t a = -40 to +105 c, 2.4 v ? v dd ? 3.6 v, 2.4 v ? av refp ? av dd = v dd ? 3.6 v, v ss = 0 v, av ss = 0 v, reference voltage (+) = av refp , reference voltage (-) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 2.4 v ? av refp ? av dd ? 3.6 v 8 12 bit overall error note 1 ainl 12-bit resolution 2.4 v ? av refp ? av dd ? 3.6 v ? 7.0 lsb conversion time t conv adtyp = 0, 12-bit resolution 2.4 v ? av refp ? av dd ? 3.6 v 4.125 ? s zero-scale error note 1 e zs 12-bit resolution 2.4 v ? av refp ? av dd ? 3.6 v ? 5.0 lsb full-scale error note 1 e fs 12-bit resolution 2.4 v ? av refp ? av dd ? 3.6 v ? 5.0 lsb integral linearity error note 1 ile 12-bit resolution 2.4 v ? av refp ? av dd ? 3.6 v ? 3.0 lsb differential linearity error note 1 dle 12-bit resolution 2.4 v ? av refp ? av dd ? 3.6 v ? 2.0 lsb analog input voltage v ain 0a v refp v internal reference voltage (2.4 v ? v dd ? 3.6 v, hs (high-speed main) mode) v bgr note 2 temperature sensor output voltage (2.4 v ? v dd ? 3.6 v, hs (high-speed main) mode) v tmp25 note 2
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 136 of 149 feb 21, 2014 note 1. excludes quantization error ( ? 1/2 lsb). note 2. refer to 3.6.2 temperature sensor, internal reference voltage output characteristics . caution always use av dd pin with the same potential as the v dd pin. (4) when reference voltage (+) = av dd (adrefp1 = 0, adrefp0 = 0), reference voltage (-) = av ss (adrefm = 0), conversion target: ani16 to ani21, internal reference voltage, temperature sensor output voltage (t a = -40 to +105 c, 2.4 v ? v dd ? 3.6 v, 2.4 v ? av dd = v dd ? 3.6 v, v ss = 0 v, av ss = 0 v, reference voltage (+) = av dd , reference voltage (-) = av ss = 0) parameter symbol conditions min. typ. max. unit resolution r es 2.4 v ? av dd ? 3.6 v 8 12 bit overall error note 1 ainl 12-bit resolution 2.4 v ? av dd ? 3.6 v ? 8.5 lsb conversion time t conv adtyp = 0, 12-bit resolution 2.4 v ? av dd ? 3.6 v 4.125 ? s zero-scale error note 1 e zs 12-bit resolution 2.4 v ? av dd ? 3.6 v ? 8.0 lsb full-scale error note 1 e fs 12-bit resolution 2.4 v ? av dd ? 3.6 v ? 8.0 lsb integral linearity error note 1 ile 12-bit resolution 2.4 v ? av dd ? 3.6 v ? 3.5 lsb differential linearity error note 1 dle 12-bit resolution 2.4 v ? av dd ? 3.6 v ? 2.5 lsb analog input voltage v ain 0a v dd v internal reference voltage (2.4 v ? v dd ? 3.6 v, hs (high-speed main) mode) v bgr note 2 temperature sensor output voltage (2.4 v ? v dd ? 3.6 v, hs (high-speed main) mode) v tmp25 note 2
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 137 of 149 feb 21, 2014 note excludes quantization error (1/2 lsb). caution always use av dd pin with the same potential as the v dd pin. 3.6.2 temperature sensor, internal re ference voltage output characteristics 3.6.3 d/a converter characteristics (5) when reference voltage (+) = internal reference vo ltage (1.45 v) (adrefp1 = 1, adrefp0 = 0), reference voltage (-) = av ss (adrefm = 0), conversion targe t: ani0 to ani6, ani16 to ani21 (t a = -40 to +105 c, 2.4 v ? v dd ? 3.6 v, 2.4 v ? v dd , 2.4 v ? av dd = v dd , v ss = 0 v, av ss = 0 v, reference voltage (+) = internal reference voltage, reference voltage (-) = av ss = 0 v, hs (high-speed main) mode) parameter symbol conditions min. typ. max. unit resolution r es 8b i t conversion time t conv 8-bit resolution 16.0 ? s zero-scale error note e zs 8-bit resolution ? 4.0 lsb integral linearity error note ile 8-bit resolution ? 2.0 lsb differential linearity error note dle 8-bit resolution ? 2.5 lsb reference voltage (+) av ref(+) = internal reference voltage (v bgr ) 1.38 1.45 1.5 v analog input voltage v ain 0v bgr v (t a = -40 to +105 c, 2.4 v ? v dd ? 3.6 v, v ss = 0 v (hs (high-speed main) mode)) parameter symbol conditions min. typ. max. unit temperature sensor output voltage v tmps25 setting ads register = 80h, t a = +25 ? c1 . 0 5 v internal reference voltage v bgr setting ads register = 81h 1.38 1.45 1.5 v temperature coefficient f vtmps temperature sensor output voltage that depends on the temperature -3.6 mv/c operation stabilization wait time t amp 10 ? s (t a = -40 to +105 c, 2.4 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 8bit overall error ainl rload = 4 m ? 2.4 v ? v dd ? 3.6 v ? 2.5 lsb rload = 8 m ? 2.4 v ? v dd ? 3.6 v ? 2.5 lsb settling time t set cload = 20 pf 2.7 v ? v dd ? 3.6 v 3 ? s 2.4 v ? v dd < 2.7 v 6 ? s
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 138 of 149 feb 21, 2014 3.6.4 comparator note not usable in sub-clock operation or stop mode. 3.6.5 por circuit characteristics note minimum time required for a por reset when v dd exceeds below v pdr . this is also the minimum time required for a por reset from when v dd exceeds below 0.7 v to when v dd exceeds v por while stop mode is entered or the main system clock is stopped through setting bit 0 (hiostop) and bit 7 (mstop) in the clock operation status control register (csc). (t a = -40 to +105 c, 2.4 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit input voltage range ivref 0 v dd - 1.4 v ivcmp -0.3 v dd + 0.3 v output delay td v dd = 3.0 v input slew rate > 50 mv/ ? s high-speed comparator mode, standard mode 1.2 ? s high-speed comparator mode, window mode 2.0 ? s low-speed comparator mode, standard mode 35.0 ? s high-electric-potential judgment voltage vtw+ high-speed comparator mode, window mode 0.76 v dd v low-electric-potential judgment voltage vtw- high-speed comparator mode, window mode 0.24 v dd v operation stabilization wait time t cmp 100 ? s internal reference voltage note v bgr 2.4 v ? v dd ? 3.6 v, hs (high-speed main) mode 1.38 1.45 1.50 v (t a = -40 to +105 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage v por power supply rise time 1.45 1.51 1.57 v v pdr power supply fall time note 1.44 1.50 1.56 v minimum pulse width t pw 300 ? s t pw v por v pdr or 0.7 v supply voltage (v dd )
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 139 of 149 feb 21, 2014 3.6.6 lvd circuit characteristics caution set the detection voltage (v lvd ) to be within the operating voltage range. the operating voltage range depends on the setting of the user option byte (000c2h/010c2h). the following shows the operating voltage range. hs (high-speed main) mode: v dd = 2.7 to 3.6 v at 1 mhz to 24 mhz v dd = 2.4 to 3.6 v at 1 mhz to 16 mhz (t a = -40 to +105 c, v pdr ? v dd ? 3.6 v ? v ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage supply voltage level v lvd2 power supply rise time 3.01 3.13 3.25 v power supply fall time 2.94 3.06 3.18 v v lvd3 power supply rise time 2.90 3.02 3.14 v power supply fall time 2.85 2.96 3.07 v v lvd4 power supply rise time 2.81 2.92 3.03 v power supply fall time 2.75 2.86 2.97 v v lvd5 power supply rise time 2.71 2.81 2.92 v power supply fall time 2.64 2.75 2.86 v v lvd6 power supply rise time 2.61 2.71 2.81 v power supply fall time 2.55 2.65 2.75 v v lvd7 power supply rise time 2.51 2.61 2.71 v power supply fall time 2.45 2.55 2.65 v minimum pulse width t lw 300 ? s detection delay time 300 ? s
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 140 of 149 feb 21, 2014 3.7 power supply voltage ri sing slope ch aracteristics caution make sure to keep the internal reset state by the lvd circuit or an external reset until v dd reaches the operating voltage range shown in 3.4 ac characteristics. lvd detection voltage of interrupt & reset mode (t a = -40 to +105 c, v pdr ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit interrupt and reset mode v lvdd0 v poc0 , v poc1 , v poc2 = 0, 1, 1, falling reset voltage: 2.7 v 2.64 2.75 2.86 v v lvdd1 lvis0, lvis1 = 1, 0 rising release reset voltage 2.81 2.92 3.03 v falling interrupt voltage 2.75 2.86 2.97 v v lvdd2 lvis0, lvis1 = 0, 1 rising release reset voltage 2.90 3.02 3.14 v falling interrupt voltage 2.85 2.96 3.07 v (t a = -40 to +105 c, v ss = 0 v) parameter conditions min. typ. max. unit power supply voltage rising slope sv dd 54 v/ms
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 141 of 149 feb 21, 2014 3.8 lcd characteristics 3.8.1 resistance division method (1) static display mode (t a = -40 to +105 c, v l4 (min.) ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit lcd drive voltage v l4 2.0 v dd v (2) 1/2 bias method, 1/4 bias method (t a = -40 to +105 c, v l4 (min.) ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit lcd drive voltage v l4 2.7 v dd v (3) 1/3 bias method (t a = -40 to +105 c, v l4 (min.) ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit lcd drive voltage v l4 2.5 v dd v
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 142 of 149 feb 21, 2014 3.8.2 internal voltage boosting method note 1. this is a capacitor that is connected between voltage pins used to drive the lcd. c1: a capacitor connected between caph and capl c2: a capacitor connected between v l1 and gnd c3: a capacitor connected between v l2 and gnd c4: a capacitor connected between v l4 and gnd c1 = c2 = c3 = c4 = 0.47 ? f ? 30% note 2. this is the time required to wait from when the reference voltage is specified by using the vlcd register (or when the internal voltage boosting method is selected (by setting the mdset1 and mdset0 bits of the lcdm0 register to 01b) if the default value reference voltage is used) until voltage boosting starts (vlcon = 1). note 3. this is the wait time from when voltage boosting is star ted (vlcon = 1) until display is enabled (lcdon = 1). (1) 1/3 bias method (t a = -40 to +105 c, 2.4 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit lcd output voltage variation range v l1 c1 to c4 note 1 = 0.47 ? f note 2 vlcd = 04h 0.90 1 .00 1.08 v vlcd = 05h 0.95 1.05 1.13 v vlcd = 06h 1.00 1.1 0 1.18 v vlcd = 07h 1.05 1.15 1.23 v vlcd = 08h 1.10 1.2 0 1.28 v vlcd = 09h 1.15 1.25 1.33 v vlcd = 0ah 1.20 1.3 0 1.38 v vlcd = 0bh 1.25 1.35 1.43 v vlcd = 0ch 1.30 1.40 1.48 v vlcd = 0dh 1.35 1.45 1.53 v vlcd = 0eh 1.40 1.5 0 1.58 v vlcd = 0fh 1.45 1.55 1.63 v vlcd = 10h 1.50 1.6 0 1.68 v vlcd = 11h 1.55 1.65 1.73 v vlcd = 12h 1.60 1.7 0 1.78 v vlcd = 13h 1.65 1.75 1.83 v doubler output voltage v l2 c1 to c4 note 1 = 0.47 ? f 2 v l1 - 0.1 2 v l1 2 v l1 v tripler output voltage v l3 c1 to c4 note 1 = 0.47 ? f 3 v l1 - 0.15 3 v l1 3 v l1 v reference voltage setup time note 2 t vwait1 5m s voltage boost wait time note 3 t vwait2 c1 to c4 note 1 = 0.47 ? f 500 ms
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 143 of 149 feb 21, 2014 note 1. this is a capacitor that is connected between voltage pins used to drive the lcd. c1: a capacitor connected between caph and capl c2: a capacitor connected between v l1 and gnd c3: a capacitor connected between v l2 and gnd c4: a capacitor connected between v l3 and gnd c5: a capacitor connected between v l4 and gnd c1 = c2 = c3 = c4 = 0.47 ? f ? 30% note 2. this is the time required to wait from when the reference voltage is specified by using the vlcd register (or when the internal voltage boosting method is selected (by setting the mdset1 and mdset0 bits of the lcdm0 register to 01b) if the default value reference voltage is used) until voltage boosting starts (vlcon = 1). note 3. this is the wait time from when voltage boosting is star ted (vlcon = 1) until display is enabled (lcdon = 1). (2) 1/4 bias method (t a = -40 to +105 c, 2.4 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit lcd output voltage variation range v l1 c1 to c4 note 1 = 0.47 ? f note 2 vlcd = 04h 0.90 1 .00 1.08 v vlcd = 05h 0.95 1.05 1.13 v vlcd = 06h 1.00 1.1 0 1.18 v vlcd = 07h 1.05 1.15 1.23 v vlcd = 08h 1.10 1.2 0 1.28 v vlcd = 09h 1.15 1.25 1.33 v vlcd = 0ah 1.20 1.3 0 1.38 v doubler output voltage v l2 c1 to c4 note 1 = 0.47 ? f 2 v l1 - 0.08 2 v l1 2 v l1 v tripler output voltage v l3 c1 to c4 note 1 = 0.47 ? f 3 v l1 - 0.12 3 v l1 3 v l1 v quadruply output voltage v l4 c1 to c5 note 1 = 0.47 ? f 4 v l1 - 0.16 4 v l1 4 v l1 v reference voltage setup time note 2 t vwait1 5m s voltage boost wait time note 3 t vwait2 c1 to c5 note 1 = 0.47 ? f 500 ms
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 144 of 149 feb 21, 2014 3.8.3 capacitor split method note 1. this is the wait time from when voltage bucking is started (vlcon = 1) until display is enabled (lcdon = 1). note 2. this is a capacitor that is connected between voltage pins used to drive the lcd. c1: a capacitor connected between caph and capl c2: a capacitor connected between v l1 and gnd c3: a capacitor connected between v l2 and gnd c4: a capacitor connected between v l4 and gnd c1 = c2 = c3 = c4 = 0.47 ? f ? 30% (1) 1/3 bias method (t a = -40 to +105 c, 2.4 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit v l4 voltage v l4 c1 to c4 = 0.47 ? f note 2 v dd v v l2 voltage v l2 c1 to c4 = 0.47 ? f note 2 2/3 v l4 - 0.07 2/3 v l4 2/3 v l4 + 0.07 v v l1 voltage v l1 c1 to c4 = 0.47 ? f note 2 1/3 v l4 - 0.08 1/3 v l4 1/3 v l4 + 0.08 v capacitor split wait time note 1 t vwait 100 ms
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 145 of 149 feb 21, 2014 3.9 data memory stop mode low supply voltage data retention characteristics note the value depends on the por detection voltage. when the vo ltage drops, the data is retained before a por reset is effected, but data is not retained when a por reset is effected. 3.10 flash memory programming characteristics note 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. the retaining years are until next rewrite after the rewrite. note 2. when using flash memory programmer and renesas electronics self programming library note 3. these are the characteristics of the flash memory and the results obtained from reliability testing by renesas electronics corporation. 3.11 dedicated flash memory programmer communication (uart) (t a = -40 to +105 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.44 note 3.6 v (t a = -40 to +105 c, 2.4 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit cpu/peripheral hardware clock frequency f clk 2.4 v ? v dd ? 3.6 v 124mhz number of code flash rewrites notes 1, 2, 3 c erwr retained for 20 years t a = 85 ? c 1,000 times number of data flash rewrites notes 1, 2, 3 retained for 1 year t a = 25 ? c 1,000,000 retained for 5 years t a = 85 ? c 100,000 retained for 20 years t a = 85 ? c 10,000 (t a = -40 to +105 c, 2.4 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit transfer rate during serial programming 115,200 1,000,000 bps v dd stop instruction execution standby release signal (interrupt request) stop mode data retention mode operation mode v dddr
rl78/l1c 3. electrical specifications (g: t a = -40 to +105 c) r01ds0192ej0200 rev. 2.00 page 146 of 149 feb 21, 2014 3.12 timing specs for switching modes <1> the low level is input to the tool0 pin. <2> the external reset ends (por and lvd reset must end before the external reset ends.). <3> the tool0 pin is set to the high level. <4> setting of the flash memory programming mode by uart reception and complete the baud rate setting. remark t suinit : the segment shows that it is necessary to finish spec ifying the initial communication settings within 100 ms from when the resets end. t su : how long from when the tool0 pin is placed at the low level until a external reset ends t hd: how long to keep the tool0 pin at the low level from when the external and internal resets end (except soft processing time) (t a = -40 to +105 c, 2.4 v ? v dd ? 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit how long from when an external reset ends until the initial communication se ttings are specified t suinit por and lvd reset must end before the external reset ends. 100 ms how long from when the tool0 pin is placed at the low level until an external reset ends t su por and lvd reset must end before the external reset ends. 10 ? s time to hold the tool0 pin at the low level after an external reset is released (excluding the processing time of the firmware to control the flash memory) t hd por and lvd reset must end before the external reset ends. 1ms reset tool0 <1> <2> <3> t su <4> t suinit 723 s + t hd processing time 00h reception (toolrxd, tooltxd mode)
rl78/l1c 4. package drawings r01ds0192ej0200 rev. 2.00 page 147 of 149 feb 21, 2014 4. package drawings 4.1 80-pin products r5f110meafb, r5f110mfafb, r5f110mgafb, r5f110mhafb, R5F110MJafb r5f111meafb, r5f111mfafb, r5f111mgafb, r5f111mhafb, r5f111mjafb r5f110megfb, r5f110mfgfb, r5f110mggfb, r5f110mhgfb, R5F110MJgfb r5f111megfb, r5f111mfgfb, r5f111mggfb, r5f111mhgfb, r5f111mjgfb detail f c a l 1 l a 1 a 2 index mark *2 *1 *3 f 80 61 60 41 40 21 20 1 x z e z d e h e d h d e b p 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. previous code jeita package code renesas code plqp0080kb-a 80p6q-a mass[typ.] 0.5g p-lfqfp80-12x12-0.50 1.0 0.125 0.18 1.25 1.25 0.08 0.20 0.1450.09 0.250.200.15 max nom min dimension in millimeters symbol reference 12.112.011.9 d 12.112.011.9 e 1.4 a 2 14.214.013.8 14.214.013.8 1.7 a 0.20.1 0 0.70.50.3 l x 10 0 c 0.5 e 0.08 y h d h e a 1 b p b 1 c 1 z d z e l 1 terminal cross section c bp c 1 b 1 y s s
rl78/l1c 4. package drawings r01ds0192ej0200 rev. 2.00 page 148 of 149 feb 21, 2014 4.2 85-pin products r5f110neala, r5f110nfala, r5f110ngala, r5f110nhala, r5f110njala r5f111neala, r5f111nfala, r5f111ngala, r5f111nhala, r5f111njala r5f110negla, r5f110nfgla, r5f110n ggla, r5f110nhgla, r5f110njgla r5f111negla, r5f111nfgla, r5f111nggla, r5f111nhgla, r5f111njgla 2013 renesas electronics corporation. all rights reserved. a s jeita package code renesas code previous code mass(typ.)[g] p-vflga85-7x7-0.65 pvlg0085ja-a p85fc-65-bn4 0.1 index area d b 0.575 0.35 7.00 7.00 referance symbol min nom max dimension in millimeters 0.30 0.40 x a 1.00 y 0.10 e z y z 1 d e e 0.65 0.08 0.20 0.575 7.10 6.90 7.10 6.90 y1 s s y s x b a b m s wa s wb z a b e d c a d e f b 5 7 9 46 8 10 2 3 1 z d e a g h j k a detail b 0.45 0.05 (land size) (sr opening size) e w 0.20
rl78/l1c 4. package drawings r01ds0192ej0200 rev. 2.00 page 149 of 149 feb 21, 2014 4.3 100-pin products r5f110peafb, r5f110pfafb, r5f110pgafb, r5f110phafb, r5f110pjafb r5f111peafb, r5f111pfafb, r5f111pgafb, r5f111phafb, r5f111pjafb r5f110pegfb, r5f110pfgfb, r5f110pggfb, r5f110phgfb, r5f110pjgfb r5f111pegfb, r5f111pfgfb, r5f111pggfb, r5f111phgfb, r5f111pjgfb terminal cross section b 1 c 1 b p c 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. index mark x 12 5 26 50 51 75 76 100 f *1 *3 *2 z e z d e d h d h e b p detail f l 1 a 2 a 1 l a c l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.08 e 0.5 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 15.8 16.0 16.2 15.8 16.0 16.2 a 2 1.4 e 13.9 14.0 14.1 d 13.9 14.0 14.1 reference symbol dimension in millimeters min nom max 0.15 0.20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 previous code jeita package code renesas code plqp0100kb-a 100p6q-a / fp-100u / fp-100uv mass[typ.] 0.6g p-lfqfp100-14x14-0.50 e y s s
c - 1 rl78/l1c datasheet rev. date description page summary 0.01 oct 15, 2012 ? first edition issued 1.00 nov 18, 2013 1, 2 modification of 1.1 features 3, 4 modification of 1.2 ordering information 5 to 8 modification of package type in 1.3 pin configuration (top view) 14 to 17 modification of vectored interr upt sources in 1.6 outline of functions 14 to 17 modification of operating ambien t temperature in 1.6 outline of functions 19 to 21 modification of description in tables in 2.1 absolute maximum ratings 22, 23 modification of description in 2.2 oscillator characteristics 25 modification of low-level output cu rrent in 2.3.1 pin characteristics 26 modification of error of high-level input voltage conditions in 2.3.1 pin characteristics 26 modification of error of low-level in put voltage conditions in 2.3.1 pin characteristics 27 modification of low-level output voltage in 2.3.1 pin characteristics 28 modification of error of internal pul l-up resistor conditions in 2.3.1 pin characteristics 29 to 34 modification of 2.3.2 supply current characteristics 35, 36 modification of 2.4 ac characteristics 37, 38 addition of minimum instruction execution time during main system clock operation 41 to 63 addition of ls mode and lv mode characteristics in 2.5.1 serial array unit 64 to 66 addition of ls mode and lv mode char acteristics in 2.5.2 serial interface iica 67, 68 modification of conditions in 2.5.3 usb 69 addition of (3) bc optio n standard in 2.5.3 usb 70 to 75 addition of characteristics about c onversion of internal reference voltage and temperature sensor in 2.6.1 a/d converter characteristics 76 addition of characteristic in 2.6.4 comparator 76 deletion of detection delay in 2. 6.5 por circuit characteristics 78 modification of 2.7 power supply voltage rising slope characteristics 79 to 82 modification of 2.8 lcd characteristics 83 modification of 2.9 data memory stop mode low supply voltage data retention characteristics 83 modification of 2.10 flash memory programming characteristics 84 addition of 2.12 timing specs for switching modes 85 to 144 addition of 3. electrical specifications (g: t a = -40 to +105c) 2.00 feb 21, 2014 all addition of 85-pin product information all modification from 80-pin to 80/85-pin all modification from x = m, p to x = m, n, p all modification from high-accuracy real-time clock to real-time clock 2 all modification from rtc to rtc2 1 modification of 1.1 features 3 modification of 1.2 ordering information revision history
revision history rl78/l1c datasheet c - 2 2.00 feb 21, 2014 4 modification of figure 1 - 1 part number, memory size, and package of rl78/l1c 69 modification of (1) electrical specifications in 2.5.3 usb 82 modification of note 1 in (1) 1/3 bias method in 2.8.2 internal voltage boosting method 130 modification of (1) electrical specifications in 3.5.3 usb 142 modification of note 1 in (1) 1/3 bias method in 3.8.2 internal voltage boosting method rev. date description page summary superflash is a registered trademark of silicon storage technology, inc. in several countries including the united states and japan. caution: this product uses superflash ? technology licensed from s ilicon storage technology, inc. all trademarks and registered trademarks ar e the property of their respective owners.
notes for cmos devices (1) voltage application waveform at input pin: waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between vil (max) and vih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between vil (max) and vih (min). (2) handling of unused input pins: unconnected cm os device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an in ternal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd via a resist or if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) precaution against esd: a strong electric fi eld, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade t he device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequat e. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be gr ounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touc hed with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. (4) status before initialization: power-on does not necessarily define the in itial status of a mos device. immediately after the power source is turn ed on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o setti ngs or contents of registers. a device is not initialized un til the reset signal is received. a re set operation must be executed immediately after power-on for devices with reset functions. (5) power on/off sequence: in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the po wer supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) input of signal during power off state : do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that re sults from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal cu rrent that passes in the device at this time may cause degradation of internal elem ents. input of signals during th e power off state must be judged separately for each device and according to re lated specifications governing the device.
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